Add PortAPI between IO and Harness blocks

generators/chipyard/src/main/scala/clocking/ClockBinders.scala

@@ -2,17 +2,13 @@ package chipyard.clocking
 
 import chisel3._
 import chisel3.util._
-import chipyard.iobinders.{OverrideLazyIOBinder, GetSystemParameters, IOCellKey}
+import chipyard.iobinders.{OverrideLazyIOBinder, GetSystemParameters, IOCellKey, ClockPort, ResetPort}
 import freechips.rocketchip.prci._
 import freechips.rocketchip.diplomacy._
 import freechips.rocketchip.subsystem._
 import freechips.rocketchip.tilelink._
 import barstools.iocell.chisel._
 
-class ClockWithFreq(val freqMHz: Double) extends Bundle {
-  val clock = Clock()
-}
-
 // This uses the FakePLL, which uses a ClockAtFreq Verilog blackbox to generate
 // the requested clocks. This also adds TileLink ClockDivider and ClockSelector
 // blocks, which allow memory-mapped control of clock division, and clock muxing
@@ -58,13 +54,13 @@ class WithPLLSelectorDividerClockGenerator extends OverrideLazyIOBinder({
     pllCtrlSink := pllCtrl.ctrlNode
 
     InModuleBody {
-      val clock_wire = Wire(Input(new ClockWithFreq(100)))
+      val clock_wire = Wire(Input(Clock()))
       val reset_wire = Wire(Input(AsyncReset()))
       val (clock_io, clockIOCell) = IOCell.generateIOFromSignal(clock_wire, "clock", p(IOCellKey))
       val (reset_io, resetIOCell) = IOCell.generateIOFromSignal(reset_wire, "reset", p(IOCellKey))
 
       slowClockSource.out.unzip._1.map { o =>
-        o.clock := clock_wire.clock
+        o.clock := clock_wire
         o.reset := reset_wire
       }
 
@@ -79,7 +75,7 @@ class WithPLLSelectorDividerClockGenerator extends OverrideLazyIOBinder({
         o.reset := reset_wire
       }
 
-      (Seq(clock_io, reset_io), clockIOCell ++ resetIOCell)
+      (Seq(ClockPort(clock_io, 100), ResetPort(reset_io)), clockIOCell ++ resetIOCell)
     }
   }
 })
@@ -114,12 +110,12 @@ class WithPassthroughClockGenerator extends OverrideLazyIOBinder({
         require(m.take.isDefined, s"""Clock ${m.name.get} has no requested frequency
                                      |Clocks: ${edge.sink.members.map(_.name.get)}""".stripMargin)
         val freq = m.take.get.freqMHz
-        val clock_io = IO(Input(new ClockWithFreq(freq))).suggestName(s"clock_${m.name.get}")
-        b.clock := clock_io.clock
+        val clock_io = IO(Input(Clock())).suggestName(s"clock_${m.name.get}")
+        b.clock := clock_io
         b.reset := reset_io
-        clock_io
+        ClockPort(clock_io, freq)
       }.toSeq
-      ((clock_ios :+ reset_io), Nil)
+      ((clock_ios :+ ResetPort(reset_io)), Nil)
     }
   }
 })

generators/chipyard/src/main/scala/config/AbstractConfig.scala

@@ -15,15 +15,17 @@ class AbstractConfig extends Config(
   new chipyard.harness.WithUARTAdapter ++                          // add UART adapter to display UART on stdout, if uart is present
   new chipyard.harness.WithBlackBoxSimMem ++                       // add SimDRAM DRAM model for axi4 backing memory, if axi4 mem is enabled
   new chipyard.harness.WithSimTSIOverSerialTL ++                   // add external serial-adapter and RAM
-  new chipyard.harness.WithSimDebug ++                             // add SimJTAG or SimDTM adapters if debug module is enabled
+  new chipyard.harness.WithSimJTAGDebug ++                         // add SimJTAG if JTAG for debug exposed
+  new chipyard.harness.WithSimDMI ++                               // add SimJTAG if DMI exposed
   new chipyard.harness.WithGPIOTiedOff ++                          // tie-off chiptop GPIOs, if GPIOs are present
   new chipyard.harness.WithSimSPIFlashModel ++                     // add simulated SPI flash memory, if SPI is enabled
   new chipyard.harness.WithSimAXIMMIO ++                           // add SimAXIMem for axi4 mmio port, if enabled
   new chipyard.harness.WithTieOffInterrupts ++                     // tie-off interrupt ports, if present
   new chipyard.harness.WithTieOffL2FBusAXI ++                      // tie-off external AXI4 master, if present
   new chipyard.harness.WithCustomBootPinPlusArg ++                 // drive custom-boot pin with a plusarg, if custom-boot-pin is present
   new chipyard.harness.WithSimUARTToUARTTSI ++                     // connect a SimUART to the UART-TSI port
-  new chipyard.harness.WithClockAndResetFromHarness ++             // all Clock/Reset I/O in ChipTop should be driven by harnessClockInstantiator
+  new chipyard.harness.WithClockFromHarness ++                     // all Clock I/O in ChipTop should be driven by harnessClockInstantiator
+  new chipyard.harness.WithResetFromHarness ++                     // reset controlled by harness
   new chipyard.harness.WithAbsoluteFreqHarnessClockInstantiator ++ // generate clocks in harness with unsynthesizable ClockSourceAtFreqMHz
 
   // The IOBinders instantiate ChipTop IOs to match desired digital IOs

generators/chipyard/src/main/scala/config/TracegenConfigs.scala

@@ -7,7 +7,8 @@ class AbstractTraceGenConfig extends Config(
   new chipyard.harness.WithAbsoluteFreqHarnessClockInstantiator ++
   new chipyard.harness.WithBlackBoxSimMem ++
   new chipyard.harness.WithTraceGenSuccess ++
-  new chipyard.harness.WithClockAndResetFromHarness ++
+  new chipyard.harness.WithClockFromHarness ++
+  new chipyard.harness.WithResetFromHarness ++
   new chipyard.iobinders.WithAXI4MemPunchthrough ++
   new chipyard.iobinders.WithTraceGenSuccessPunchthrough ++
   new chipyard.clocking.WithPassthroughClockGenerator ++

generators/chipyard/src/main/scala/example/FlatChipTop.scala

@@ -68,13 +68,13 @@ class FlatChipTop(implicit p: Parameters) extends LazyModule {
       l.reset := implicit_reset
     }}
 
-    val clock_wire = Wire(Input(new ClockWithFreq(80)))
+    val clock_wire = Wire(Input(Clock()))
     val reset_wire = Wire(Input(AsyncReset()))
     val (clock_pad, clockIOCell) = IOCell.generateIOFromSignal(clock_wire, "clock", p(IOCellKey))
     val (reset_pad, resetIOCell) = IOCell.generateIOFromSignal(reset_wire, "reset", p(IOCellKey))
 
     slowClockSource.out.unzip._1.map { o =>
-      o.clock := clock_wire.clock
+      o.clock := clock_wire
       o.reset := reset_wire
     }
 

generators/chipyard/src/main/scala/example/FlatTestHarness.scala

@@ -30,7 +30,7 @@ class FlatTestHarness(implicit val p: Parameters) extends Module {
   val clock_source = Module(new ClockSourceAtFreqFromPlusArg("slow_clk_freq_mhz"))
   clock_source.io.power := true.B
   clock_source.io.gate := false.B
-  dut.clock_pad.clock := clock_source.io.clk
+  dut.clock_pad := clock_source.io.clk
 
   // Reset
   dut.reset_pad := reset.asAsyncReset