Update SpikeTile isa str to include more useful extensions

ucb-bar · Jun 28, 2024 · 19fc3dd · 19fc3dd
1 parent f0875b0
commit 19fc3dd
Showing 1 changed file with 1 addition and 1 deletion.
diff --git a/generators/chipyard/src/main/scala/SpikeTile.scala b/generators/chipyard/src/main/scala/SpikeTile.scala
@@ -115,7 +115,7 @@ class SpikeTile(
   val masterNode = visibilityNode
   val slaveNode = TLIdentityNode()
 
-  override def isaDTS = "rv64gcv_Zfh"
+  override def isaDTS = "rv64imafdcv_zicsr_zifencei_zihpm_zvl128b_zve64d"
 
   // Required entry of CPU device in the device tree for interrupt purpose
   val cpuDevice: SimpleDevice = new SimpleDevice("cpu", Seq("ucb-bar,spike", "riscv")) {