Bump rocket-chip

ucb-bar · Oct 20, 2023 · 127a759 · 127a759
1 parent 1d9dba5
commit 127a759
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Showing 4 changed files with 8 additions and 5 deletions.
diff --git a/generators/chipyard/src/main/scala/config/AbstractConfig.scala b/generators/chipyard/src/main/scala/config/AbstractConfig.scala
@@ -53,7 +53,7 @@ class AbstractConfig extends Config(
 
   // By default, punch out IOs to the Harness
   new chipyard.clocking.WithPassthroughClockGenerator ++
-  new chipyard.clocking.WithClockGroupsCombinedByName(("uncore", Seq("sbus", "mbus", "pbus", "fbus", "cbus", "implicit"), Seq("tile"))) ++
+  new chipyard.clocking.WithClockGroupsCombinedByName(("uncore", Seq("sbus", "mbus", "pbus", "fbus", "cbus"), Seq("tile"))) ++
   new chipyard.config.WithPeripheryBusFrequency(500.0) ++           // Default 500 MHz pbus
   new chipyard.config.WithControlBusFrequency(500.0) ++             // Default 500 MHz cbus
   new chipyard.config.WithMemoryBusFrequency(500.0) ++              // Default 500 MHz mbus

diff --git a/generators/chipyard/src/main/scala/config/TracegenConfigs.scala b/generators/chipyard/src/main/scala/config/TracegenConfigs.scala
@@ -12,10 +12,11 @@ class AbstractTraceGenConfig extends Config(
   new chipyard.iobinders.WithAXI4MemPunchthrough ++
   new chipyard.iobinders.WithTraceGenSuccessPunchthrough ++
   new chipyard.clocking.WithPassthroughClockGenerator ++
-  new chipyard.clocking.WithClockGroupsCombinedByName(("uncore", Seq("sbus", "implicit"), Nil)) ++
+  new chipyard.clocking.WithClockGroupsCombinedByName(("uncore", Seq("sbus"), Nil)) ++
   new chipyard.config.WithTracegenSystem ++
   new chipyard.config.WithNoSubsystemClockIO ++
   new chipyard.config.WithMemoryBusFrequency(1000.0) ++
+  new chipyard.config.WithControlBusFrequency(1000.0) ++
   new chipyard.config.WithSystemBusFrequency(1000.0) ++
   new chipyard.config.WithPeripheryBusFrequency(1000.0) ++
   new freechips.rocketchip.subsystem.WithCoherentBusTopology ++

diff --git a/generators/rocket-chip b/generators/rocket-chip
diff --git a/generators/tracegen/src/main/scala/System.scala b/generators/tracegen/src/main/scala/System.scala
@@ -23,11 +23,13 @@ class TraceGenSystem(implicit p: Parameters) extends BaseSubsystem
     case t: BoomTraceGenTile => t.statusNode.makeSink()
   }
 
+  lazy val fakeClockDomain = sbus.generateSynchronousDomain
+
   lazy val clintOpt = None
   lazy val debugOpt = None
   lazy val plicOpt = None
-  lazy val clintDomainOpt = None
-  lazy val plicDomainOpt = None
+  lazy val clintDomainOpt = Some(fakeClockDomain)
+  lazy val plicDomainOpt = Some(fakeClockDomain)
 
   override lazy val module = new TraceGenSystemModuleImp(this)
 }
+8 −6		src/main/scala/interrupts/Crossing.scala
+2 −2		src/main/scala/interrupts/NullIntSource.scala
+4 −4		src/main/scala/subsystem/HasHierarchicalElements.scala
+1 −1		src/main/scala/tilelink/BusWrapper.scala