# https://www.sphinx-doc.org/en/master/usage/configuration.html
 
 # -- Project information -----------------------------------------------------
 # https://www.sphinx-doc.org/en/master/usage/configuration.html#project-information
 
-project = 'Seal5'
-copyright = '2024, TUM Department of Electrical and Computer Engineering - Chair of Electronic Design Automation'
-author = 'TUM Department of Electrical and Computer Engineering - Chair of Electronic Design Automation'
-release = 'v0.1.0'
+project = "Seal5"
+copyright = "2024, TUM Department of Electrical and Computer Engineering - Chair of Electronic Design Automation"
+author = "TUM Department of Electrical and Computer Engineering - Chair of Electronic Design Automation"
+release = "v0.1.0"
 
 # -- General configuration ---------------------------------------------------
 # https://www.sphinx-doc.org/en/master/usage/configuration.html#general-configuration
 
-extensions = ["sphinx.ext.autodoc", "sphinx.ext.autosummary", "sphinx.ext.viewcode", "myst_parser", "numpydoc", "sphinxemoji.sphinxemoji"]
+extensions = [
+    "sphinx.ext.autodoc",
+    "sphinx.ext.autosummary",
+    "sphinx.ext.viewcode",
+    "myst_parser",
+    "numpydoc",
+    "sphinxemoji.sphinxemoji",
+]
 numpydoc_show_class_members = False
 autosummary_generate = True  # Turn on sphinx.ext.autosummary
 
-templates_path = ['_templates']
-exclude_patterns = ['_build', 'Thumbs.db', '.DS_Store']
+templates_path = ["_templates"]
+exclude_patterns = ["_build", "Thumbs.db", ".DS_Store"]
 
-root_doc = 'index'
+root_doc = "index"
 
 
 # -- Options for HTML output -------------------------------------------------
 # https://www.sphinx-doc.org/en/master/usage/configuration.html#options-for-html-output
 
 # html_theme = 'alabaster'
-html_theme = 'sphinx_rtd_theme'
-html_static_path = ['_static']
+html_theme = "sphinx_rtd_theme"
+html_static_path = ["_static"]

                             reg_class = model.Seal5RegisterClass.CSR
                         else:
                             assert offset == 0  # TODO: write offset to Operand class?
                             reg_class = model.Seal5RegisterClass.UNKNOWN
                         if not isinstance(op, model.Seal5RegOperand):
-                            op = model.Seal5RegOperand(op.name, op.ty, op.attributes, op.constraints, reg_class=reg_class)
+                            op = model.Seal5RegOperand(
+                                op.name, op.ty, op.attributes, op.constraints, reg_class=reg_class
+                            )
                         reg_ty = model.Seal5Type(arch.DataType.U, mem_size, mem_lanes)
                         op.reg_ty = reg_ty
                         context.operands[op_name] = op
                 elif isinstance(index_left, behav.BinaryOperation):
                     # print("index_left -> binop")

                     if index_left.op.value == "+":
                         # print("op.value -> +")
                         offset = None
                         # print("il.l", index_left.left)
                         # print("il.r", index_left.right)
-                        if isinstance(index_left.left, behav.NamedReference) and isinstance(index_left.left.reference, arch.BitFieldDescr):
+                        if isinstance(index_left.left, behav.NamedReference) and isinstance(
+                            index_left.left.reference, arch.BitFieldDescr
+                        ):
                             # print("index_left.left -> bfr")
                             assert index_left.left.reference.name == op_name, "slice base register missmatch"
                             if isinstance(index_left.right, behav.IntLiteral):
                                 offset = index_left.right.value
-                        elif isinstance(index_left.right, behav.NamedReference) and isinstance(index_left.right.reference, arch.BitFieldDescr):
+                        elif isinstance(index_left.right, behav.NamedReference) and isinstance(
+                            index_left.right.reference, arch.BitFieldDescr
+                        ):
                             # print("index_left.right -> bfr")
                             assert index_left.right.reference.name == op_name, "slice base register missmatch"
                             if isinstance(index_left.left, behav.IntLiteral):
                                 offset = index_left.left.value
                         else:

                         reg_class = model.Seal5RegisterClass.GPR32Pair
                         # print("reg_class", reg_class)
                         # print("op", op)
                         if not isinstance(op, model.Seal5RegOperand):
                             # print("not is")
-                            op = model.Seal5RegOperand(op.name, op.ty, op.attributes, op.constraints, reg_class=reg_class)
+                            op = model.Seal5RegOperand(
+                                op.name, op.ty, op.attributes, op.constraints, reg_class=reg_class
+                            )
                         else:
                             pass
                             # print("skipping")  # TODO: check for conflicts
                         # print("op_", op)
                         # input("124")