# Load test inputs
 test_files = [
     # EXAMPLES_DIR / "tests" / "xcorev" / "cv_abs.test.c",
     # EXAMPLES_DIR / "tests" / "corev" / "*.asm.s",
     # EXAMPLES_DIR / "tests" / "corev" / "*.invalid-asm.s",
-    EXAMPLES_DIR / "tests" / "corev" / "*.inline-asm.c",
+    EXAMPLES_DIR
+    / "tests"
+    / "corev"
+    / "*.inline-asm.c",
 ]
 seal5_flow.load(test_files, verbose=VERBOSE, overwrite=True)
 
 # Load YAML inputs
 cfg_files = [

 )
 
 # Load CoreDSL inputs
 cdsl_files = [
     # EXAMPLES_DIR / "cdsl" / "rv_gen" / "all_v7.core_desc",
-    EXAMPLES_DIR / "cdsl" / "rv_gen" / "all_v9.core_desc",
+    EXAMPLES_DIR
+    / "cdsl"
+    / "rv_gen"
+    / "all_v9.core_desc",
 ]
 seal5_flow.load(cdsl_files, verbose=VERBOSE, overwrite=True)
 
 # Load test inputs
-test_files = [
-]
+test_files = []
 seal5_flow.load(test_files, verbose=VERBOSE, overwrite=True)
 
 # Load YAML inputs
 cfg_files = [
     # GENERATED

             ("collect_immediate_operands", passes.collect_immediate_operands, {}),
             ("collect_operand_types", passes.collect_operand_types, {}),
             ("detect_side_effects", passes.detect_side_effects, {}),
             ("detect_inouts", passes.detect_inouts, {}),
             ("detect_registers", passes.detect_registers, {}),
-            ("write_cdsl_full", passes.write_cdsl, {"split": False, "compat": False})
+            ("write_cdsl_full", passes.write_cdsl, {"split": False, "compat": False}),
             # TODO: determine static constraints (xlen,...) -> subtargetvmap
             # detect memory adressing modes
             # self.detect_adressing_modes(verbose)  # TODO
             # detect legal GMIR ops (and map to selectiondag?)
             # self.detect_legal_ops(verbose=verbose)  # TODO