Merge pull request #85 from tum-ei-eda/tidy-up

Tidy up

examples/cdsl/Example.core_desc → examples/cdsl/rv_example/Example.core_desc

@@ -1,4 +1,4 @@
-import "rv_base/RV32I.core_desc"
+import "../rv_base/RV32I.core_desc"
 
 // InstructionSet XExample extends RISCVBase {
 InstructionSet XExample extends RV32I {

examples/demo.py

@@ -62,12 +62,14 @@
 
 # Load CoreDSL inputs
 cdsl_files = [
-    EXAMPLES_DIR / "cdsl" / "Example.core_desc",
+    EXAMPLES_DIR / "cdsl" / "rv_example" / "Example.core_desc",
 ]
 seal5_flow.load(cdsl_files, verbose=VERBOSE, overwrite=True)
 
 # Load test inputs
-test_files = []
+test_files = [
+    EXAMPLES_DIR / "tests" / "example" / "test_subincacc.c",
+]
 seal5_flow.load(test_files, verbose=VERBOSE, overwrite=True)
 
 # Load YAML inputs

examples/tests/example/test_subincacc.c

@@ -0,0 +1,25 @@
+// Test the SubIncAcc instruction of the TUM "example" extension.
+// After calling the function the value 10 should be present in
+// register a0, where an integer return value would be expected
+//
+// Compile with the "example" extension specified:
+//   clang test_subincacc.c -c --target=riscv32 -march=rv32ixexample
+// then disassembly shows the new instruction:
+//   llvm-objdump -d test_subincacc.o --disassembler-options=numeric
+
+// For automated runs by llvm-lit:
+// RUN: clang -c -target riscv32-unknown-elf -march=rv32ixexample -o %t.o %s
+// RUN: llvm-objdump --disassembler-options=numeric -d %t.o | FileCheck %s
+
+
+__attribute__((naked)) void test_subincacc() {
+    // Non-ISAX canary instruction, to flag an unwanted case of endian/width/compression/whatever
+    // CHECK: b3 01 52 00 add x3, x4, x5
+    asm("add x3, x4, x5");
+
+    asm("li a0, 11");
+    asm("li a1, 5");
+    asm("li a2, 7");
+    // CHECK: ab ba b5 51 cv_subincacc x21, x11, x27
+    asm("cv_subincacc x21, x11, x27");
+}