fix the bug that for block_k=16 mma, the compilation crash on Ampere. #4768

bingyizh233 · 2024-09-20T06:26:05Z

The origin issue is reported here #3435: The issue happens during compilation, when arith.sitofp (from i8 to fp16) operates on the tensor operand which has dot_op layout with the first dimension of the tensor being 16 and opidx = 1. For example: %104 = arith.sitofp %103 : tensor<16x64xi8, #triton_gpu.dot_op<{opIdx = 1, parent = #mma, kWidth = 4}>> to tensor<16x64xf16, #triton_gpu.dot_op<{opIdx = 1, parent = #mma, kWidth = 4}>> Investigation shows that the bug happens in TritonGPUToLLVM pass. in the corner case (block_k = 16 and opidx = 1) extra elements will be unpacked in include/triton/Conversion/TritonGPUToLLVM/ElementwiseOpToLLVM.h:line (here). The code unpack extra elements due to an implicit assumption in lib/Dialect/TritonGPU/IR/Dialect.h, at here, at least 4 rep will be loaded. Therefore, in our patch, extra loaded elements are dropped in the corner case.

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The origin issue is reported here: triton-lang#3435 The issue happens during compilation, when arith.sitofp (from i8 to fp16) operates on the tensor operand which has dot_op layout with the first dimension of the tensor being 16 and opidx = 1. For example: %104 = arith.sitofp %103 : tensor<16x64xi8, #triton_gpu.dot_op<{opIdx = 1, parent = #mma, kWidth = 4}>> to tensor<16x64xf16, #triton_gpu.dot_op<{opIdx = 1, parent = #mma, kWidth = 4}>> Investigation shows that the bug happens in TritonGPUToLLVM pass. in the corner case (block_k = 16 and opidx = 1) extra elements will be unpacked in include/triton/Conversion/TritonGPUToLLVM/ElementwiseOpToLLVM.h:line 186-194. The code unpack extra elements due to an implicit assumption in lib/Dialect/TritonGPU/IR/Dialect.h, at line 2000, at least 4 rep will be loaded. Therefore, in our patch, extra loaded elements are dropped in the corner case.

Jokeren · 2024-09-20T12:13:33Z

Hi, thanks for your information. However, a PR like this is not acceptable.

Most importantly, I don't see any test case included

gflegar · 2024-09-20T16:30:18Z

We can take a first pass at this from the Google side, since we asked Nvidia for help with this, and once it's in an acceptable state we will assign to a core maintainer for final approval. @Moerafaat can take a first look (unfortunately, I don't think I can assign him officially as the reviewer), since he's most familiar with that part of the codebase. And then @chsigg can serve as the final quality gate, as agreed between OAI & Google.

bingyizh233 · 2024-09-20T16:48:22Z

Hi, thanks for your information. However, a PR like this is not acceptable.

Most importantly, I don't see any test case included

Thank you for your feedback! I’ll work on adding the test cases. Additionally, could you please let me know if there’s anything else that might be missing?

Jokeren · 2024-09-20T17:03:53Z

The mixed precision stuff is quite fragile as far as I know. I'm not sure as I haven't been taken a look for a while.

test/Conversion/tritongpu_to_llvm_ampere.mlir.TYhis This is a the test case for converting tensor from s8 to fp16 when the first dimension of the tensor==16 and opidx==1. Previously, the compilation could crash during convert-triton-gpu-llvm on Nvidia Ampere GPU. The new code patch resolves the issue. This new test case is to verify the crash does not exist.

This is a the test case for converting tensor from s8 to fp16 when the first dimension of the tensor==16 and opidx==1. Previously, the compilation could crash during convert-triton-gpu-llvm on Nvidia Ampere GPU. The new code patch resolves the issue. This new test case is to verify the crash does not exist

Moerafaat · 2024-09-23T09:36:40Z

Thanks for the effort here, I will take a deeper look. Just a few notes for now:

Can you please provide a permalink for this? "lib/Dialect/TritonGPU/IR/Dialect.h, at line 2000, at least 4 rep will be loaded."
At the time of reporting the issue, this was one instance of failures that happened due to "size mismatch during packing in LLVM". Can you verify that the matmul with swapped input order works, i.e. S8xF16 ?
The way we currently work around this issue is in the auto-tuner. It is currently handled in a generic way (i.e. not specific to S8 for example). You can see here that we are disabling tiling configurations that would potentially lead to running into this issue. Ideally a solution would be accepted if we can remove this restriction in the auto-tuner without any failing tests. Can you include this as part of your change as well and see if we get any failures? Also note that we have a similar restriction here for sparsity that we would like to remove as well.

Moerafaat · 2024-09-23T14:03:44Z

I was also trying to see other scenarios that we ran into that could be classified as the same issue. For example, looking at this sample HLO:

triton_dot {
  parameter = f8e4m3fn[32,32]{1,0} parameter(0)
  parameter.1 = f8e4m3fn[32,32]{1,0} parameter(1)
  ROOT dot = f32[32,32]{1,0} dot(parameter,parameter.1), lhs_contracting_dims={1}, rhs_contracting_dims={0}
}

ENTRY e {
  parameter = f8e4m3fn[32,32]{1,0} parameter(0)
  parameter.1 = f8e4m3fn[32,32]{1,0} parameter(1)
  ROOT dot = f32[32,32]{1,0} fusion(parameter,parameter.1), kind=kCustom, calls=triton_dot,
    backend_config={"fusion_backend_config":{kind: "__triton_gemm", triton_gemm_config: {"block_m":16,"block_n":16,"block_k":16,"split_k":1,"num_stages":2,"num_warps":2,"num_ctas":1}}}

With your change this will fail with the same "size mismatch" error. I suspect that in this case it would be because the adjustment will not apply to the left-hand side because of the restriction on the OpIdx. Is that restriction necessary or is something else the reason for failing in this example?

Moerafaat · 2024-09-23T14:24:57Z

Another example where the current solution would fail is for this example:

  parameter_0 = s8[64,64]{1,0} parameter(0)
  convert.2 = bf16[64,64]{1,0} convert(parameter_0)
  parameter_1 = bf16[128,32]{1,0} parameter(1)
  parameter_2 = u16[64,8]{1,0} parameter(2)
  ROOT dot.0 = bf16[64,32]{1,0} dot(convert.2, parameter_1, parameter_2), lhs_contracting_dims={1}, rhs_contracting_dims={0}, sparsity=L.1@2:4

This one goes through tt.sparse_dot (only exists if you use XLA's Triton). It's fine if you can't reproduce this example, but what I could also observe with this example for some tilings (for example shape[0] = 64, shape[1] = 16 for OpIdx = 0) is that this will also run into the same failure. So I'm questioning if the condition strictly applies for shape[0]?

Moerafaat · 2024-09-23T14:33:14Z

Also make sure to run pre-commit on the change.

Moerafaat · 2024-09-23T14:28:02Z

python/test/unit/ampere/test_gemm_mixed_dtype.py

+        [128, 128, 128, 64, 16, 16, torch.float16, torch.int8]
+    ])
+@pytest.mark.skipif(torch.cuda.get_device_capability()[0] != 8, reason="Requires compute capability == 8")
+def test_gemm_mixed_dtype(M, N, K, block_m, block_n, block_k, dtype_a, dtype_b):


Can you leave a comment explaining the purpose of this test? There are mixed-type tests that exist. The emphasis here should be focused on mixed-types with small tile sizes. I would suggest also renaming the file to indicate emphasis on small tiles.

Also can we add more variety in the parametrization? Perhaps use fp8 types as well instead of just int8.

Moerafaat · 2024-09-23T14:28:30Z

test/Conversion/tritongpu_to_llvm_ampere.mlir

+
+#mma = #triton_gpu.nvidia_mma<{versionMajor = 2, versionMinor = 0, warpsPerCTA = [2, 2], instrShape = [16, 8]}>
+module attributes {"triton_gpu.num-ctas" = 1 : i32, "triton_gpu.num-warps" = 4 : i32, triton_gpu.shared = 3072 : i32, triton_gpu.target = "cuda:80", "triton_gpu.threads-per-warp" = 32 : i32} {
+  tt.func public @amperes8tofp16conversion(%1 : tensor<16x32xi8, #triton_gpu.dot_op<{opIdx = 1, parent = #mma, kWidth = 4}>>) attributes {noinline = false} {


Nit: Triton's conversion on the naming here is snake_case. Please adjust.

Have adjusted the naming following snake_case and added a test case when 'opIdx == 1 and shape[1] == 16'.

Moerafaat · 2024-09-23T14:30:56Z

lib/Conversion/TritonGPUToLLVM/ElementwiseOpToLLVM.cpp

-      ret.push_back(values[i + 13]);
-      ret.push_back(values[i + 14]);
-      ret.push_back(values[i + 15]);
+    if(in_shape[0] == 16 && inEncoding.getOpIdx() == 1){  // In the corner case where in_shape[0] == 16 and getOpIdx() == 1, extra elements will be loaded. It is necessary to discard these additional elements.


As I mentioned in the comments I left on the PR, I'm questioning the condition here as some cases will not match this and fail for the same reason.

I tried to change this condition to
in_shape[0] == 16 || out_shape == 16 instead, and it passes the 2 cases I indicated previously that fail. That being said, I'm not sure if this is the correct way to handle it or not.

Thanks for the information. I have looked into this. The condition to (in_shape[0] == 16 && inEncoding.getOpIdx() == 1) && (in_shape[1] == 16 && inEncoding.getOpIdx() == 0) resolve the issues and might be a better way, including s8xfp16 case. I will look at the other cases you mentions.

Moerafaat · 2024-09-23T14:32:14Z

lib/Conversion/TritonGPUToLLVM/ElementwiseOpToLLVM.cpp

@@ -56,23 +58,37 @@ SmallVector<Value> reorderValues(const SmallVector<Value> &values, Type inType,
  }
  if (inBitWidth == 8 && ouBitWidth == 16) {


Is this fix only applicable to conversions from 8-bit to 16-bit or is this extendable to other combinations as well?

This only works for the conversions from 8-bit to 16-bit. Other datatype (e.g., 32-bit) has different data layout for triton_gpu.dot_op.

bingyizh233 · 2024-09-23T17:59:35Z

Thanks for the effort here, I will take a deeper look. Just a few notes for now:

Can you please provide a permalink for this? "lib/Dialect/TritonGPU/IR/Dialect.h, at line 2000, at least 4 rep will be loaded."

At the time of reporting the issue, this was one instance of failures that happened due to "size mismatch during packing in LLVM". Can you verify that the matmul with swapped input order works, i.e. S8xF16 ?

The way we currently work around this issue is in the auto-tuner. It is currently handled in a generic way (i.e. not specific to S8 for example). You can see here that we are disabling tiling configurations that would potentially lead to running into this issue. Ideally a solution would be accepted if we can remove this restriction in the auto-tuner without any failing tests. Can you include this as part of your change as well and see if we get any failures? Also note that we have a similar restriction here for sparsity that we would like to remove as well.

Thanks for the detailed comments. I update the commit log by adding the permalink. I will test other cases and take a deep look into it. Could you provide an example code for running this gemm_fusion_autotuner ?

bingyizh233 · 2024-09-24T00:11:33Z

Thanks for the effort here, I will take a deeper look. Just a few notes for now:

Can you please provide a permalink for this? "lib/Dialect/TritonGPU/IR/Dialect.h, at line 2000, at least 4 rep will be loaded."

At the time of reporting the issue, this was one instance of failures that happened due to "size mismatch during packing in LLVM". Can you verify that the matmul with swapped input order works, i.e. S8xF16 ?

The way we currently work around this issue is in the auto-tuner. It is currently handled in a generic way (i.e. not specific to S8 for example). You can see here that we are disabling tiling configurations that would potentially lead to running into this issue. Ideally a solution would be accepted if we can remove this restriction in the auto-tuner without any failing tests. Can you include this as part of your change as well and see if we get any failures? Also note that we have a similar restriction here for sparsity that we would like to remove as well.

Can I ask what is the data tiling configurations restriction in here besides triton's restriction? As far as I know, triton has the restriction that block_m >=16, block_n >=16, block_k>=16, and block_m, block_n, block_k should be power 2. Besides the triton restriction and (block_k != 16) which leads to crash. What is other restriction in the autotuner? Thanks!

Moerafaat · 2024-09-24T12:09:29Z

Thanks for the effort here, I will take a deeper look. Just a few notes for now:

Can you please provide a permalink for this? "lib/Dialect/TritonGPU/IR/Dialect.h, at line 2000, at least 4 rep will be loaded."

At the time of reporting the issue, this was one instance of failures that happened due to "size mismatch during packing in LLVM". Can you verify that the matmul with swapped input order works, i.e. S8xF16 ?

The way we currently work around this issue is in the auto-tuner. It is currently handled in a generic way (i.e. not specific to S8 for example). You can see here that we are disabling tiling configurations that would potentially lead to running into this issue. Ideally a solution would be accepted if we can remove this restriction in the auto-tuner without any failing tests. Can you include this as part of your change as well and see if we get any failures? Also note that we have a similar restriction here for sparsity that we would like to remove as well.

Thanks for the detailed comments. I update the commit log by adding the permalink. I will test other cases and take a deep look into it. Could you provide an example code for running this gemm_fusion_autotuner ?

You can run tests here that are purposed for this. You don't have to worry about coverage for now, I can test internally and report to you other issues if they arise.

Moerafaat · 2024-09-24T12:14:33Z

Thanks for the effort here, I will take a deeper look. Just a few notes for now:

Can you please provide a permalink for this? "lib/Dialect/TritonGPU/IR/Dialect.h, at line 2000, at least 4 rep will be loaded."

At the time of reporting the issue, this was one instance of failures that happened due to "size mismatch during packing in LLVM". Can you verify that the matmul with swapped input order works, i.e. S8xF16 ?

The way we currently work around this issue is in the auto-tuner. It is currently handled in a generic way (i.e. not specific to S8 for example). You can see here that we are disabling tiling configurations that would potentially lead to running into this issue. Ideally a solution would be accepted if we can remove this restriction in the auto-tuner without any failing tests. Can you include this as part of your change as well and see if we get any failures? Also note that we have a similar restriction here for sparsity that we would like to remove as well.

Can I ask what is the data tiling configurations restriction in here besides triton's restriction? As far as I know, triton has the restriction that block_m >=16, block_n >=16, block_k>=16, and block_m, block_n, block_k should be power 2. Besides the triton restriction and (block_k != 16) which leads to crash. What is other restriction in the autotuner? Thanks!

The restriction here is Triton specific only at the mentioned line. The idea here is that block_k = 16 is specific to cases where we have 8-bit width types. The way it is written here is just the generalization for any bit-width.

chsigg · 2024-09-26T12:54:57Z

lib/Conversion/TritonGPUToLLVM/ElementwiseOpToLLVM.cpp

-      ret.push_back(values[i + 13]);
-      ret.push_back(values[i + 14]);
-      ret.push_back(values[i + 15]);
+    if ((in_shape[0] == 16 && inEncoding.getOpIdx() == 1) ||


I think this would be more readable:

bool loadsExtraElements = in_shape[1-inEncoding.getOpIdx()] == 16; for (unsigned i = 0; i < values.size(); i += 16) { ret.push_back(values[i + 0]); ret.push_back(values[i + 1]); ret.push_back(values[i + 2]); ret.push_back(values[i + 3]); ret.push_back(values[i + 8]); ret.push_back(values[i + 9]); ret.push_back(values[i + 10]); ret.push_back(values[i + 11]); if (loadsExtraElements) continue; // Discard elements that aren't needed. ret.push_back(values[i + 4]); ret.push_back(values[i + 5]); ret.push_back(values[i + 6]); ret.push_back(values[i + 7]); ret.push_back(values[i + 12]); ret.push_back(values[i + 13]); ret.push_back(values[i + 14]); ret.push_back(values[i + 15]); }

Thanks for the suggestions. I have restructured the code in the newest commit. All the test and pre-commit have been done again.

Moerafaat · 2024-09-26T13:08:07Z

After addressing the last comment from @chsigg I think the PR would be ready for OAI to have a look.

bingyizh233 · 2024-09-26T20:07:39Z

After addressing the last comment from @chsigg I think the PR would be ready for OAI to have a look.

I have restructured the code in the newest commit. All the test and pre-commit have been done again.

chsigg · 2024-09-27T14:39:12Z

@Jokeren, this should be ready for review now. Would you mind to take a look? Thanks!

Jokeren · 2024-10-01T12:39:24Z

cc @ThomasRaoux

ThomasRaoux · 2024-10-01T13:53:49Z

This seems like a very ad hoc workaround for the crash.
It is clear we need to re-work this as we shouldn't have to move data around when doing type conversion. This code is definitely a workaround for a more fundamental problem with dot_encoding layouts. I'm a bit concerns about adding more hack on top of of the existing hack to make things work.

I assume you are not blocked by this on the XLA side as you have this patch already?
Would you be interested in helping doing a proper fix for the dot_encoding layout instead? WDYT?

Jokeren · 2024-10-02T14:43:26Z

IMHO, I think it's fine to merge if it's an urgent issue that prevents you guys from moving forward, and we can use your code as a reference while we're refactoring the dot operand layout.

Moerafaat · 2024-10-02T18:03:08Z

@ThomasRaoux it is indeed working around the issue, but not in an invasive manner I would say as the change is small and local. We work around it in XLA by entirely omitting tiling configurations that include such cases. We really would like to include these sizes in our tiling configs and this fix will allow us to do so.

We have many cases where we maintain some fixes internally (some are hacks), but ideally where we can, it would be great to have the changes upstream to minimize the differences. This allows us to also monitor issues and collaborate easily if this diff is smaller.

Moerafaat · 2024-10-21T11:46:24Z

@ThomasRaoux just a friendly ping on this thread when you have time to take a look :)

bingyizh233 · 2024-10-24T18:52:27Z

Trying to do rebase and test it on Ampere. However, currently pytest of upstream has errors on ampere platform. Report the issue here #4990

Jokeren · 2024-10-29T23:30:26Z

lib/Conversion/TritonGPUToLLVM/ElementwiseOpToLLVM.cpp

      ret.push_back(values[i + 6]);
      ret.push_back(values[i + 7]);
+      if (loadsExtraElements)


You can also repeat extra elements

Sorry, I did not get the words "repeat extra elements". Any clarification is appreciated. Thanks!

Push i=0 to 7 again into ret

ret.push_back(values[i]); ret.push_back(values[i + 1]); ret.push_back(values[i + 4]); ret.push_back(values[i + 5]); ret.push_back(values[i + 2]); ret.push_back(values[i + 3]); ret.push_back(values[i + 6]); ret.push_back(values[i + 7]); if (loadsExtraElements){ ret.push_back(values[i]); ret.push_back(values[i + 1]); ret.push_back(values[i + 4]); ret.push_back(values[i + 5]); ret.push_back(values[i + 2]); ret.push_back(values[i + 3]); ret.push_back(values[i + 6]); ret.push_back(values[i + 7]); continue; // Discard elements that aren't needed. }

I just tried to push the i=0 -7 again. However, it gives error when testing python/test/unit/ampere/test_gemm_mixed_dtype_small_tile.py. Here, packing extra elements may cause unmatch for number of registers.

@Jokeren I'm not sure I understand what you mean. The intent of the change is to actually not pack the extra elements as they result in a size mismatch during lowering to LLVM.

Let's wait a bit until this PR has been landed. #5044

Maybe a lot of issues you guys saw previously will be gone

We merged this change internally (via a patch) for now as we are facing issues now with Triton at main (including the change in #5044.

I'll look into it today

…ut types involve an 8-bit. This change is porting in this [PR](triton-lang/triton#4768). PiperOrigin-RevId: 695275077

…ut types involve an 8-bit. This change is porting in this [PR](triton-lang/triton#4768). PiperOrigin-RevId: 695311919

bingyizh233 requested a review from ptillet as a code owner September 20, 2024 06:26

gflegar assigned gflegar and unassigned gflegar Sep 20, 2024

gflegar requested review from chsigg and removed request for ptillet September 20, 2024 16:26

gflegar mentioned this pull request Sep 20, 2024

fix the bug that for block_k=16 mma, the compilation crash on Ampere. openxla/triton#15

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gflegar marked this pull request as draft September 20, 2024 16:36

bingyizh233 added 3 commits September 20, 2024 20:12

Moerafaat reviewed Sep 23, 2024

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Support the case where LHS is 8 bit and convert LHS into 16 bit

c6407ac

bingyizh233 added 5 commits September 24, 2024 18:02

add python unit test for mixed dtype gemm 16bitx8bit and 8bitx16bit

b70082f

renaming the old test file

2c63c38

add lit test for small tile size gemm with mixed dtype bing s8xfp16

d37d0b7

add comments for new added python test cases

3b85c79

Merge remote-tracking branch 'upstream/main'

68f49dc

bingyizh233 added 2 commits September 25, 2024 20:14

add comments in test_gemm_mixed_dtype_small_tile.py

9a6682e

Merge remote-tracking branch 'upstream/main'

8ec8b8c

chsigg reviewed Sep 26, 2024

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bingyizh233 added 2 commits September 26, 2024 19:48

Merge remote-tracking branch 'upstream/main'

1006afb

Restructure the code in ElementwiseOpToLLVM.h for fixing the crash issue

bcbd1f7

Merge branch 'main' into main

2635acd

chsigg marked this pull request as ready for review September 27, 2024 14:38

Merge branch 'main' into main

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Jokeren reviewed Oct 29, 2024

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copybara-service bot mentioned this pull request Nov 11, 2024

[Triton] Fix a bug while lowering to LLVM for block_k=16 when the input types involve an 8-bit. This change is porting in this [PR](https://github.com/triton-lang/triton/pull/4768). openxla/xla#19225

Merged

copybara-service bot mentioned this pull request Nov 11, 2024

[Triton] Fix a bug while lowering to LLVM for block_k=16 when the input types involve an 8-bit. This change is porting in this [PR](https://github.com/triton-lang/triton/pull/4768). tensorflow/tensorflow#79783

Merged

		@@ -56,23 +58,37 @@ SmallVector<Value> reorderValues(const SmallVector<Value> &values, Type inType,
		}
		if (inBitWidth == 8 && ouBitWidth == 16) {

fix the bug that for block_k=16 mma, the compilation crash on Ampere. #4768

Are you sure you want to change the base?

fix the bug that for block_k=16 mma, the compilation crash on Ampere. #4768

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bingyizh233 commented Sep 20, 2024 •

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