VIP for AXI Protocol

Waveform Viewer Extension for VScode

uvm examples and source code

UVM Test bench for a 8-bit ALU

BDD Gherkin implementation in native SystemVerilog, based on UVM.

VIP for I2C

Design Verification of Flash, UART, and SDRAM controller for a 32 bit embedded RISC microprocessor using cocotb.

Basic UVM Testbench to verify AXI stream spec design. Added a wishbone BFM to mimic Wishbone design.

Sleipnir is a tool for randomizing software data types in python. It is designed to help aid design verification of complex SoC designs. This repo contains the sleipnir tool and a set of examples.

design-and-verification-of-MCDF-phase3

design-and-verification-of-MCDF-phase4

Moore.io Demo Project

Code for a train gate STPA model that uses simulink design verifier, arduino and blender

AXI Verif IP development

This repository contain all the necessary files to verify PISO Universal Register

Tabular digital waveform viewer as a TUI

This repository contains an extensive learning journey of FPGA

This repository contains System Verilog codes. These codes were written while learning system verilog. Will be updated almost daily as I learn more and more

Batch JIRA Goodness for Designers