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timemeansalot/README.md
  • 👋 Hi, I’m 'timemeansalot'
  • 👀 I’m interested in Computer Science and Digital IC
  • 🌱 I’m currently learning DSP, Data Structure, Algorithm and Verilog
  • 💞️ I’m looking to collaborate on do some projects in the above areas
  • 📫 How to reach me: you can contact me through github Issus

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  1. FAST_INTR_CPU FAST_INTR_CPU Public

    Forked from ChipDesign/FAST_INTR_CPU

    Verilog 1

  2. ChipDesign/FAST_INTR_CPU ChipDesign/FAST_INTR_CPU Public

    Verilog 3

  3. SourceFiles SourceFiles Public

    TeX

  4. cs-notes cs-notes Public

    Lua

  5. env_config env_config Public

    Lua