arch/risc-v/src/mpfs/mpfs_ddr.c: Make sure that DDRC is in reset when…

… starting the training Also move the DDRC clock enablement and reset to mpfs_init_ddr. This doesn't change the functionality, but is the cleaner place for it. Signed-off-by: Jukka Laitinen <[email protected]>
tiiuae · Aug 25, 2023 · 2602afd · 2602afd
1 parent 1f9b2ba
commit 2602afd
Showing 1 changed file with 13 additions and 10 deletions.
diff --git a/arch/risc-v/src/mpfs/mpfs_ddr.c b/arch/risc-v/src/mpfs/mpfs_ddr.c
@@ -812,6 +812,19 @@ void mpfs_setup_ddr_segments(enum seg_setup_e option)
 
 static void mpfs_init_ddrc(void)
 {
+  /* Turn on DDRC clock */
+
+  modifyreg32(MPFS_SYSREG_SUBBLK_CLOCK_CR, 0,
+              SYSREG_SUBBLK_CLOCK_CR_DDRC);
+
+  /* Remove soft reset */
+
+  modifyreg32(MPFS_SYSREG_SOFT_RESET_CR, 0,
+              SYSREG_SUBBLK_CLOCK_CR_DDRC);
+
+  modifyreg32(MPFS_SYSREG_SOFT_RESET_CR,
+              SYSREG_SUBBLK_CLOCK_CR_DDRC, 0);
+
   putreg32(LIBERO_SETTING_CFG_MANUAL_ADDRESS_MAP,
            MPFS_DDR_CSR_APB_CFG_MANUAL_ADDRESS_MAP);
   putreg32(LIBERO_SETTING_CFG_CHIPADDR_MAP,
@@ -3130,16 +3143,6 @@ static int mpfs_set_mode_vs_bits(struct mpfs_ddr_priv_s *priv)
 
   mpfs_setup_ddr_segments(DEFAULT_SEG_SETUP);
 
-  /* Turn on DDRC clock */
-
-  modifyreg32(MPFS_SYSREG_SUBBLK_CLOCK_CR, 0,
-              SYSREG_SUBBLK_CLOCK_CR_DDRC);
-
-  /* Remove soft reset */
-
-  modifyreg32(MPFS_SYSREG_SOFT_RESET_CR,
-              SYSREG_SUBBLK_CLOCK_CR_DDRC, 0);
-
   /* Set-up DDRC */
 
   mpfs_init_ddrc();