Merge branch 'master' into support-gcc12-filename-macro

tianocore · Sep 13, 2024 · 3a9486c · 3a9486c
2 parents eef43c7 + 69139e3
commit 3a9486c
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diff --git a/ArmPkg/ArmPkg.dsc b/ArmPkg/ArmPkg.dsc
@@ -93,24 +93,21 @@
 
   OemMiscLib|ArmPkg/Universal/Smbios/OemMiscLibNull/OemMiscLibNull.inf
 
+[LibraryClasses.common.SEC]
+  # ARM platforms have SEC modules with standard entry points, so we can generically link StackCheckLib
+  NULL|MdePkg/Library/StackCheckLibNull/StackCheckLibNull.inf
+
 [LibraryClasses.common.PEIM]
   HobLib|MdePkg/Library/PeiHobLib/PeiHobLib.inf
   PeimEntryPoint|MdePkg/Library/PeimEntryPoint/PeimEntryPoint.inf
   MemoryAllocationLib|MdePkg/Library/PeiMemoryAllocationLib/PeiMemoryAllocationLib.inf
   PeiServicesLib|MdePkg/Library/PeiServicesLib/PeiServicesLib.inf
   PeiServicesTablePointerLib|MdePkg/Library/PeiServicesTablePointerLib/PeiServicesTablePointerLib.inf
 
-[LibraryClasses.ARM, LibraryClasses.AARCH64]
-  NULL|ArmPkg/Library/CompilerIntrinsicsLib/CompilerIntrinsicsLib.inf
-
-  # Add support for GCC stack protector
-  NULL|MdePkg/Library/BaseStackCheckLib/BaseStackCheckLib.inf
-
 [Components.common]
   ArmPkg/Library/ArmCacheMaintenanceLib/ArmCacheMaintenanceLib.inf
   ArmPkg/Library/ArmDisassemblerLib/ArmDisassemblerLib.inf
   ArmPkg/Library/ArmPsciResetSystemLib/ArmPsciResetSystemLib.inf
-  ArmPkg/Library/CompilerIntrinsicsLib/CompilerIntrinsicsLib.inf
   ArmPkg/Library/DebugAgentSymbolsBaseLib/DebugAgentSymbolsBaseLib.inf
   ArmPkg/Library/DebugPeCoffExtraActionLib/DebugPeCoffExtraActionLib.inf
   ArmPkg/Library/DefaultExceptionHandlerLib/DefaultExceptionHandlerLib.inf

diff --git a/ArmPkg/Drivers/ArmCrashDumpDxe/ArmCrashDumpDxe.dsc b/ArmPkg/Drivers/ArmCrashDumpDxe/ArmCrashDumpDxe.dsc
@@ -43,8 +43,5 @@
   UefiLib|MdePkg/Library/UefiLib/UefiLib.inf
   UefiRuntimeServicesTableLib|MdePkg/Library/UefiRuntimeServicesTableLib/UefiRuntimeServicesTableLib.inf
 
-  NULL|ArmPkg/Library/CompilerIntrinsicsLib/CompilerIntrinsicsLib.inf
-  NULL|MdePkg/Library/BaseStackCheckLib/BaseStackCheckLib.inf
-
 [Components.common]
   ArmPkg/Drivers/ArmCrashDumpDxe/ArmCrashDumpDxe.inf
diff --git a/ArmPkg/Drivers/ArmGic/GicV3/AArch64/ArmGicV3.S b/ArmPkg/Drivers/ArmGic/GicV3/AArch64/ArmGicV3.S
@@ -5,7 +5,7 @@
 #
 #
 
-#include <AsmMacroIoLibV8.h>
+#include <AsmMacroLib.h>
 
 #if !defined(__clang__)
 

diff --git a/ArmPkg/Drivers/ArmGic/GicV3/Arm/ArmGicV3.S b/ArmPkg/Drivers/ArmGic/GicV3/Arm/ArmGicV3.S
@@ -5,7 +5,7 @@
 #
 #
 
-#include <AsmMacroIoLib.h>
+#include <AsmMacroLib.h>
 #include <Library/ArmLib.h>
 
 // For the moment we assume this will run in SVC mode on ARMv7

diff --git a/ArmPkg/Drivers/ArmPsciMpServicesDxe/MpFuncs.S b/ArmPkg/Drivers/ArmPsciMpServicesDxe/MpFuncs.S
@@ -7,7 +7,7 @@
 .text
 .align 3
 
-#include <AsmMacroIoLibV8.h>
+#include <AsmMacroLib.h>
 #include <IndustryStandard/ArmStdSmc.h>
 #include <Library/ArmLib.h>
 

diff --git a/ArmPkg/Include/AsmMacroIoLib.inc b/ArmPkg/Include/AsmMacroIoLib.inc
diff --git a/ArmPkg/Library/ArmExceptionLib/AArch64/ExceptionSupport.S b/ArmPkg/Library/ArmExceptionLib/AArch64/ExceptionSupport.S
@@ -9,7 +9,7 @@
 
 #include <AArch64/AArch64.h>
 #include <Library/PcdLib.h>
-#include <AsmMacroIoLibV8.h>
+#include <AsmMacroLib.h>
 #include <Protocol/DebugSupport.h> // for exception type definitions
 
 /*

diff --git a/ArmPkg/Library/ArmHvcLib/AArch64/ArmHvc.S b/ArmPkg/Library/ArmHvcLib/AArch64/ArmHvc.S
@@ -6,7 +6,7 @@
 //
 //
 
-#include <AsmMacroIoLibV8.h>
+#include <AsmMacroLib.h>
 
 ASM_FUNC(ArmCallHvc)
   // Push x0 on the stack - The stack must always be quad-word aligned

diff --git a/ArmPkg/Library/ArmHvcLib/Arm/ArmHvc.S b/ArmPkg/Library/ArmHvcLib/Arm/ArmHvc.S
@@ -6,7 +6,7 @@
 //
 //
 
-#include <AsmMacroIoLib.h>
+#include <AsmMacroLib.h>
 
 .arch_extension virt
 

diff --git a/ArmPkg/Library/ArmLib/AArch64/AArch64ArchTimerSupport.S b/ArmPkg/Library/ArmLib/AArch64/AArch64ArchTimerSupport.S
@@ -7,7 +7,7 @@
 #
 #------------------------------------------------------------------------------
 
-#include <AsmMacroIoLibV8.h>
+#include <AsmMacroLib.h>
 
 ASM_FUNC(ArmReadCntFrq)
   mrs   x0, cntfrq_el0           // Read CNTFRQ

diff --git a/ArmPkg/Library/ArmLib/AArch64/AArch64Lib.c b/ArmPkg/Library/ArmLib/AArch64/AArch64Lib.c
@@ -18,61 +18,6 @@
 #include "AArch64Lib.h"
 #include "ArmLibPrivate.h"
 
-VOID
-AArch64DataCacheOperation (
-  IN  AARCH64_CACHE_OPERATION  DataCacheOperation
-  )
-{
-  UINTN  SavedInterruptState;
-
-  SavedInterruptState = ArmGetInterruptState ();
-  ArmDisableInterrupts ();
-
-  AArch64AllDataCachesOperation (DataCacheOperation);
-
-  ArmDataSynchronizationBarrier ();
-
-  if (SavedInterruptState) {
-    ArmEnableInterrupts ();
-  }
-}
-
-VOID
-EFIAPI
-ArmInvalidateDataCache (
-  VOID
-  )
-{
-  ASSERT (!ArmMmuEnabled ());
-
-  ArmDataSynchronizationBarrier ();
-  AArch64DataCacheOperation (ArmInvalidateDataCacheEntryBySetWay);
-}
-
-VOID
-EFIAPI
-ArmCleanInvalidateDataCache (
-  VOID
-  )
-{
-  ASSERT (!ArmMmuEnabled ());
-
-  ArmDataSynchronizationBarrier ();
-  AArch64DataCacheOperation (ArmCleanInvalidateDataCacheEntryBySetWay);
-}
-
-VOID
-EFIAPI
-ArmCleanDataCache (
-  VOID
-  )
-{
-  ASSERT (!ArmMmuEnabled ());
-
-  ArmDataSynchronizationBarrier ();
-  AArch64DataCacheOperation (ArmCleanDataCacheEntryBySetWay);
-}
-
 /**
   Check whether the CPU supports the GIC system register interface (any version)
 

diff --git a/ArmPkg/Library/ArmLib/AArch64/AArch64Lib.h b/ArmPkg/Library/ArmLib/AArch64/AArch64Lib.h
@@ -11,33 +11,6 @@
 #ifndef AARCH64_LIB_H_
 #define AARCH64_LIB_H_
 
-typedef VOID (*AARCH64_CACHE_OPERATION)(
-  UINTN
-  );
-
-VOID
-AArch64AllDataCachesOperation (
-  IN  AARCH64_CACHE_OPERATION  DataCacheOperation
-  );
-
-VOID
-EFIAPI
-ArmInvalidateDataCacheEntryBySetWay (
-  IN  UINTN  SetWayFormat
-  );
-
-VOID
-EFIAPI
-ArmCleanDataCacheEntryBySetWay (
-  IN  UINTN  SetWayFormat
-  );
-
-VOID
-EFIAPI
-ArmCleanInvalidateDataCacheEntryBySetWay (
-  IN  UINTN  SetWayFormat
-  );
-
 UINTN
 EFIAPI
 ArmReadIdAA64Dfr0 (

diff --git a/ArmPkg/Library/ArmLib/AArch64/AArch64Support.S b/ArmPkg/Library/ArmLib/AArch64/AArch64Support.S
@@ -10,7 +10,7 @@
 #------------------------------------------------------------------------------
 
 #include <AArch64/AArch64.h>
-#include <AsmMacroIoLibV8.h>
+#include <AsmMacroLib.h>
 
 .set CTRL_M_BIT,      (1 << 0)
 .set CTRL_A_BIT,      (1 << 1)
@@ -43,22 +43,6 @@ ASM_FUNC(ArmCleanInvalidateDataCacheEntryByMVA)
   dc      civac, x0   // Clean and invalidate single data cache line
   ret
 
-
-ASM_FUNC(ArmInvalidateDataCacheEntryBySetWay)
-  dc      isw, x0     // Invalidate this line
-  ret
-
-
-ASM_FUNC(ArmCleanInvalidateDataCacheEntryBySetWay)
-  dc      cisw, x0    // Clean and Invalidate this line
-  ret
-
-
-ASM_FUNC(ArmCleanDataCacheEntryBySetWay)
-  dc      csw, x0     // Clean this line
-  ret
-
-
 ASM_FUNC(ArmInvalidateInstructionCache)
   ic      iallu       // Invalidate entire instruction cache
   dsb     sy
@@ -257,65 +241,6 @@ ASM_FUNC(ArmDisableBranchPrediction)
   ret
 
 
-ASM_FUNC(AArch64AllDataCachesOperation)
-// We can use regs 0-7 and 9-15 without having to save/restore.
-// Save our link register on the stack. - The stack must always be quad-word aligned
-  stp   x29, x30, [sp, #-16]!
-  mov   x29, sp
-  mov   x1, x0                  // Save Function call in x1
-  mrs   x6, clidr_el1           // Read EL1 CLIDR
-  and   x3, x6, #0x7000000      // Mask out all but Level of Coherency (LoC)
-  lsr   x3, x3, #23             // Left align cache level value - the level is shifted by 1 to the
-                                // right to ease the access to CSSELR and the Set/Way operation.
-  cbz   x3, L_Finished          // No need to clean if LoC is 0
-  mov   x10, #0                 // Start clean at cache level 0
-
-Loop1:
-  add   x2, x10, x10, lsr #1    // Work out 3x cachelevel for cache info
-  lsr   x12, x6, x2             // bottom 3 bits are the Cache type for this level
-  and   x12, x12, #7            // get those 3 bits alone
-  cmp   x12, #2                 // what cache at this level?
-  b.lt  L_Skip                  // no cache or only instruction cache at this level
-  msr   csselr_el1, x10         // write the Cache Size selection register with current level (CSSELR)
-  isb                           // isb to sync the change to the CacheSizeID reg
-  mrs   x12, ccsidr_el1         // reads current Cache Size ID register (CCSIDR)
-  and   x2, x12, #0x7           // extract the line length field
-  add   x2, x2, #4              // add 4 for the line length offset (log2 16 bytes)
-  mov   x4, #0x400
-  sub   x4, x4, #1
-  and   x4, x4, x12, lsr #3     // x4 is the max number on the way size (right aligned)
-  clz   w5, w4                  // w5 is the bit position of the way size increment
-  mov   x7, #0x00008000
-  sub   x7, x7, #1
-  and   x7, x7, x12, lsr #13    // x7 is the max number of the index size (right aligned)
-
-Loop2:
-  mov   x9, x4                  // x9 working copy of the max way size (right aligned)
-
-Loop3:
-  lsl   x11, x9, x5
-  orr   x0, x10, x11            // factor in the way number and cache number
-  lsl   x11, x7, x2
-  orr   x0, x0, x11             // factor in the index number
-
-  blr   x1                      // Goto requested cache operation
-
-  subs  x9, x9, #1              // decrement the way number
-  b.ge  Loop3
-  subs  x7, x7, #1              // decrement the index
-  b.ge  Loop2
-L_Skip:
-  add   x10, x10, #2            // increment the cache number
-  cmp   x3, x10
-  b.gt  Loop1
-
-L_Finished:
-  dsb   sy
-  isb
-  ldp   x29, x30, [sp], #0x10
-  ret
-
-
 ASM_FUNC(ArmDataMemoryBarrier)
   dmb   sy
   ret

diff --git a/ArmPkg/Library/ArmLib/AArch64/ArmLibSupport.S b/ArmPkg/Library/ArmLib/AArch64/ArmLibSupport.S
@@ -8,7 +8,7 @@
 #
 #------------------------------------------------------------------------------
 
-#include <AsmMacroIoLibV8.h>
+#include <AsmMacroLib.h>
 
 .set DAIF_RD_FIQ_BIT,   (1 << 6)
 .set DAIF_RD_IRQ_BIT,   (1 << 7)

diff --git a/ArmPkg/Library/ArmLib/AArch64/ArmLibSupportV8.S b/ArmPkg/Library/ArmLib/AArch64/ArmLibSupportV8.S
@@ -8,7 +8,7 @@
 #
 #------------------------------------------------------------------------------
 
-#include <AsmMacroIoLibV8.h>
+#include <AsmMacroLib.h>
 
 .set MPIDR_U_BIT,    (30)
 .set MPIDR_U_MASK,   (1 << MPIDR_U_BIT)

diff --git a/ArmPkg/Library/ArmLib/Arm/ArmLibSupport.S b/ArmPkg/Library/ArmLib/Arm/ArmLibSupport.S
@@ -8,7 +8,7 @@
 #
 #------------------------------------------------------------------------------
 
-#include <AsmMacroIoLib.h>
+#include <AsmMacroLib.h>
 
 ASM_FUNC(ArmReadMidr)
   mrc     p15,0,R0,c0,c0,0

diff --git a/ArmPkg/Library/ArmLib/Arm/ArmLibSupportV7.S b/ArmPkg/Library/ArmLib/Arm/ArmLibSupportV7.S
@@ -8,7 +8,7 @@
 #
 #------------------------------------------------------------------------------
 
-#include <AsmMacroIoLib.h>
+#include <AsmMacroLib.h>
 
 ASM_FUNC(ArmIsMpCore)
   mrc     p15,0,R0,c0,c0,5

diff --git a/ArmPkg/Library/ArmLib/Arm/ArmV7ArchTimerSupport.S b/ArmPkg/Library/ArmLib/Arm/ArmV7ArchTimerSupport.S
@@ -7,7 +7,7 @@
 #
 #------------------------------------------------------------------------------
 
-#include <AsmMacroIoLib.h>
+#include <AsmMacroLib.h>
 
 ASM_FUNC(ArmReadCntFrq)
   mrc    p15, 0, r0, c14, c0, 0    @ Read CNTFRQ