intel/adlrvp: Add sub-regions to SI_ME in chromeos.fmd

This change adds sub-regions to SI_ME in chromeos.fmd. These are required to support stitching of CSE components. BUG=b:189177538 Change-Id: Ife48aafcec43555175aad44f8b6307beeaea9184 Signed-off-by: Furquan Shaikh <[email protected]> Reviewed-on: https://review.coreboot.org/c/coreboot/+/58592 Reviewed-by: Tim Wawrzynczak <[email protected]> Tested-by: build bot (Jenkins) <[email protected]>
td36 · Oct 26, 2021 · d06c091 · d06c091
1 parent 10796d8
commit d06c091
Showing 1 changed file with 9 additions and 3 deletions.
diff --git a/src/mainboard/intel/adlrvp/chromeos.fmd b/src/mainboard/intel/adlrvp/chromeos.fmd
@@ -1,14 +1,20 @@
 FLASH 32M {
 	SI_ALL 6M {
 		SI_DESC 4K
-		SI_ME
+		SI_ME {
+			CSE_LAYOUT 8K
+			CSE_RO 1588K
+			CSE_DATA 512K
+			# 64-KiB aligned to optimize RW erases during CSE update.
+			CSE_RW 4032K
+		}
 	}
 	SI_BIOS 26M {
 		RW_SECTION_A 8M {
 			VBLOCK_A 64K
 			FW_MAIN_A(CBFS)
 			RW_FWID_A 64
-			ME_RW_A(CBFS) 3M
+			ME_RW_A(CBFS) 4032K
 		}
 		RW_LEGACY(CBFS) 1M
 		RW_MISC 1M {
@@ -32,7 +38,7 @@ FLASH 32M {
 			VBLOCK_B 64K
 			FW_MAIN_B(CBFS)
 			RW_FWID_B 64
-			ME_RW_B(CBFS) 3M
+			ME_RW_B(CBFS) 4032K
 		}
 		# Make WP_RO region align with SPI vendor
 		# memory protected range specification.