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  1. tastynoob.github.io tastynoob.github.io Public

    个人博客网站

    HTML

  2. ritter-soc ritter-soc Public

    a 4-pipeline riscv soc ( included core, periph), based with rv32im ,designed by verilog

    Verilog 20 5

  3. shinezyy/gem5_data_proc shinezyy/gem5_data_proc Public

    data preprocessing scripts for gem5 output

    Python 14 12

  4. aura-core aura-core Public

    "aura" my super-scalar O3 cpu core

    SystemVerilog 24

  5. riscv-isa-sim riscv-isa-sim Public

    Forked from OpenXiangShan/riscv-isa-sim

    Spike, a RISC-V ISA Simulator

    C

  6. TOYSOC TOYSOC Public

    这是一个简单的状态机riscv cpu,使用verilog设计,用于启明星智能组暑期培训

    C 3