Support C-SKY (experimental)

.github/.cspell/project-dictionary.txt

@@ -16,6 +16,7 @@ cdsg
 CDSY
 cinc
 clrex
+cmpne
 cmpw
 cmpxchg
 cset
@@ -41,6 +42,7 @@ ldar
 ldarx
 ldaxp
 ldclrp
+ldex
 ldiapp
 ldrd
 ldrex
@@ -103,6 +105,7 @@ sreg
 srlv
 stbar
 stdcx
+stex
 stilp
 stlxp
 stpq

.github/workflows/ci.yml

@@ -138,6 +138,9 @@ jobs:
             target: armeb-unknown-linux-gnueabi
           - rust: nightly
             target: armeb-unknown-linux-gnueabi
+          # TODO
+          # - rust: nightly
+          #   target: csky-unknown-linux-gnuabiv2
           - rust: '1.59' # LLVM 13
             target: i586-unknown-linux-gnu
           - rust: '1.74' # LLVM 17 (oldest version that MaybeUninit register is supported)

README.md

@@ -45,6 +45,7 @@ Currently, x86, x86_64, Arm, AArch64, RISC-V, LoongArch64, Arm64EC, s390x, MIPS,
 | hexagon \[8] (experimental)     | isize,usize,i8,u8,i16,u16,i32,u32,i64,u64           | ✓          | ✓        |
 | m68k \[8] (experimental)        | isize,usize,i8,u8,i16,u16,i32,u32                   | ✓          | ✓\[1]    |
 | xtensa \[8] (experimental)      | isize,usize,i8,u8,i16,u16,i32,u32                   | ✓          | ✓\[1]    |
+| csky \[8] (experimental)        | isize,usize,i8,u8,i16,u16,i32,u32                   | ✓          | ✓        |
 
 \[1] Arm's atomic RMW operations are not available on v6-m (thumbv6m). RISC-V's atomic RMW operations are not available on targets without the A (or G which means IMAFD) extension such as riscv32i, riscv32imc, etc. M68k's atomic RMW operations requires target-cpu M68020+ (Linux is M68020 by default). Xtensa's atomic RMW operations are not available on esp32s2.<br>
 \[2] Requires `cmpxchg16b` target feature (enabled by default on Apple and Windows (except Windows 7) targets).<br>

build.rs

@@ -106,8 +106,8 @@ fn main() {
                 }
             }
         }
-        "avr" | "hexagon" | "m68k" | "mips" | "mips32r6" | "mips64" | "mips64r6" | "msp430"
-        | "powerpc" | "powerpc64" | "xtensa" => {
+        "avr" | "csky" | "hexagon" | "m68k" | "mips" | "mips32r6" | "mips64" | "mips64r6"
+        | "msp430" | "powerpc" | "powerpc64" | "xtensa" => {
             if version.nightly && is_allowed_feature("asm_experimental_arch") {
                 println!("cargo:rustc-cfg=atomic_maybe_uninit_unstable_asm_experimental_arch");
             }

src/arch/README.md

@@ -13,7 +13,7 @@ This document describes the operations that are considered atomic by architectur
 - [s390x](#s390x)
 - [SPARC](#sparc)
 
-TODO: write sections for AArch64, Arm, Hexagon, LoongArch, MIPS, x86, Xtensa
+TODO: write sections for AArch64, Arm, C-SKY, Hexagon, LoongArch, MIPS, x86, Xtensa
 
 ## AVR
 

src/arch/cfgs/csky.rs

@@ -0,0 +1,52 @@
+// SPDX-License-Identifier: Apache-2.0 OR MIT
+
+#![allow(missing_docs)]
+
+#[macro_export]
+macro_rules! cfg_has_atomic_8 {
+    ($($tt:tt)*) => { $($tt)* };
+}
+#[macro_export]
+macro_rules! cfg_no_atomic_8 {
+    ($($tt:tt)*) => {};
+}
+#[macro_export]
+macro_rules! cfg_has_atomic_16 {
+    ($($tt:tt)*) => { $($tt)* };
+}
+#[macro_export]
+macro_rules! cfg_no_atomic_16 {
+    ($($tt:tt)*) => {};
+}
+#[macro_export]
+macro_rules! cfg_has_atomic_32 {
+    ($($tt:tt)*) => { $($tt)* };
+}
+#[macro_export]
+macro_rules! cfg_no_atomic_32 {
+    ($($tt:tt)*) => {};
+}
+#[macro_export]
+macro_rules! cfg_has_atomic_64 {
+    ($($tt:tt)*) => {};
+}
+#[macro_export]
+macro_rules! cfg_no_atomic_64 {
+    ($($tt:tt)*) => { $($tt)* };
+}
+#[macro_export]
+macro_rules! cfg_has_atomic_128 {
+    ($($tt:tt)*) => {};
+}
+#[macro_export]
+macro_rules! cfg_no_atomic_128 {
+    ($($tt:tt)*) => { $($tt)* };
+}
+#[macro_export]
+macro_rules! cfg_has_atomic_cas {
+    ($($tt:tt)*) => { $($tt)* };
+}
+#[macro_export]
+macro_rules! cfg_no_atomic_cas {
+    ($($tt:tt)*) => {};
+}