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fixed smooth scrolling, super happy version
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SCAN_7INCH is here to stay for 800x480 lcd panels

probably the scrolling fix can be backported to SCAN_5_3 as well, but I
don't think it's useful at all because that mode is really hacky
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@svofski
svofski committed Oct 18, 2024
1 parent 8a6fe5b commit 7d2d57c
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146 changes: 73 additions & 73 deletions project/tangnano9k/vector06cc/vector06cc.gprj
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Original file line number Diff line number Diff line change
Expand Up @@ -6,79 +6,79 @@
<Device name="GW1NR-9C" pn="GW1NR-LV9QN88PC6/I5">gw1nr9c-004</Device>
<FileList>
<File path="src/gowin_rpll72/gowin_rpll72.v" type="file.verilog" enable="1"/>
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<File path="C:/Gowin/projects/vector06cc/src/floppy/timer100hz.v" type="file.verilog" enable="1"/>
<File path="C:/Gowin/projects/vector06cc/src/floppy/upi_uart/uart.v" type="file.verilog" enable="0"/>
<File path="C:/Gowin/projects/vector06cc/src/floppy/verilog-6502-copy/ALU.v" type="file.verilog" enable="1"/>
<File path="C:/Gowin/projects/vector06cc/src/floppy/verilog-6502-copy/cpu.v" type="file.verilog" enable="1"/>
<File path="C:/Gowin/projects/vector06cc/src/floppy/wd1793.v" type="file.verilog" enable="1"/>
<File path="C:/Gowin/projects/vector06cc/src/i8253/8253.v" type="file.verilog" enable="1"/>
<File path="C:/Gowin/projects/vector06cc/src/keyboard/keymatrix_ram.v" type="file.verilog" enable="1"/>
<File path="C:/Gowin/projects/vector06cc/src/keyboard/ps2k.v" type="file.verilog" enable="1"/>
<File path="C:/Gowin/projects/vector06cc/src/keyboard/scan2matrix.v" type="file.verilog" enable="1"/>
<File path="C:/Gowin/projects/vector06cc/src/keyboard/vectorkeys.v" type="file.verilog" enable="0"/>
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<File path="C:/Gowin/projects/vector06cc/src/tangnano9k/psram/psram_controller.v" type="file.verilog" enable="1"/>
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<File path="C:/Gowin/projects/vector06cc/src/tangnano9k/vram.v" type="file.verilog" enable="1"/>
<File path="C:/Gowin/projects/vector06cc/src/video/framebuffer.v" type="file.verilog" enable="1"/>
<File path="C:/Gowin/projects/vector06cc/src/video/rambuffer.v" type="file.verilog" enable="1"/>
<File path="C:/Gowin/projects/vector06cc/src/video/shiftreg2.v" type="file.verilog" enable="1"/>
<File path="C:/Gowin/projects/vector06cc/src/vm80/vm80a.v" type="file.verilog" enable="1"/>
<File path="C:/Gowin/projects/vector06cc/src/T80/T80.vhd" type="file.vhdl" enable="1"/>
<File path="C:/Gowin/projects/vector06cc/src/T80/T8080se.vhd" type="file.vhdl" enable="1"/>
<File path="C:/Gowin/projects/vector06cc/src/T80/T80_ALU.vhd" type="file.vhdl" enable="1"/>
<File path="C:/Gowin/projects/vector06cc/src/T80/T80_MCode.vhd" type="file.vhdl" enable="1"/>
<File path="C:/Gowin/projects/vector06cc/src/T80/T80_Pack.vhd" type="file.vhdl" enable="1"/>
<File path="C:/Gowin/projects/vector06cc/src/T80/T80_Reg.vhd" type="file.vhdl" enable="1"/>
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<File path="C:/Gowin/projects/vector06cc/src/ay/ay8910.vhd" type="file.vhdl" enable="1"/>
<File path="C:/Gowin/projects/vector06cc/src/ay/ym2149.vhd" type="file.vhdl" enable="1"/>
<File path="C:/Gowin/projects/vector06cc/src/floppy/neo430/core/neo430_addr_gen.vhd" type="file.vhdl" enable="1" library="neo430"/>
<File path="C:/Gowin/projects/vector06cc/src/floppy/neo430/core/neo430_alu.vhd" type="file.vhdl" enable="1" library="neo430"/>
<File path="C:/Gowin/projects/vector06cc/src/floppy/neo430/core/neo430_control.vhd" type="file.vhdl" enable="1" library="neo430"/>
<File path="C:/Gowin/projects/vector06cc/src/floppy/neo430/core/neo430_cpu.vhd" type="file.vhdl" enable="1" library="neo430"/>
<File path="C:/Gowin/projects/vector06cc/src/floppy/neo430/core/neo430_package.vhd" type="file.vhdl" enable="1" library="neo430"/>
<File path="C:/Gowin/projects/vector06cc/src/floppy/neo430/core/neo430_reg_file.vhd" type="file.vhdl" enable="1" library="neo430"/>
<File path="C:/Gowin/projects/vector06cc/src/floppy/neo430/neo430_cpu_std_logic.vhd" type="file.vhdl" enable="1"/>
<File path="C:/Gowin/projects/vector06cc/src/floppy/uart/txd.vhd" type="file.vhdl" enable="1"/>
<File path="C:/Gowin/projects/vector06cc/src/i82c55/i82c55.vhd" type="file.vhdl" enable="1"/>
<File path="src/tangnano9k.cst" type="file.cst" enable="1"/>
<File path="src/vector06cc.sdc" type="file.sdc" enable="1"/>
<File path="src/clocks.rao" type="file.gao" enable="0"/>
Expand Down
1 change: 1 addition & 0 deletions src/tangnano9k/config.v
View file
Original file line number Diff line number Diff line change
Expand Up @@ -18,6 +18,7 @@

`define WITH_FLOPPY
`define WITH_OSD

//`define WITH_SDRAM
`define WITH_PSRAM // Tang Nano 9K GW1N-NR9 Q88P
//`define FLOPPYLESS_HAX // set FDC odata to $00 when compiling without floppy
Expand Down
38 changes: 22 additions & 16 deletions src/tangnano9k/video/vga_refresh.v
View file
Original file line number Diff line number Diff line change
Expand Up @@ -33,10 +33,14 @@ module vga_refresh(
output lcd_den_o,
output lcd_hsync_o,
output lcd_vsync_o,
output [9:0] lcd_y,
output lcd_newline_o, // single clock hs
output [9:0] lcd_x_o,
output [9:0] lcd_y_o,
output hsync,
output vsync,
output lcd_newline_o, // single clock lcd hsync (+)
output vga_newline_o, // single clock vga hsync (+)
output tv_newline_o, // single clock tv hsync (+)
output loadscroll_o,
output YPbPrvsync,
output videoActive,
output bordery,
Expand Down Expand Up @@ -98,6 +102,11 @@ assign lcd_clk_o = clk24;

parameter state0 = 3'b000, state1 = 3'b001, state2 = 3'b010, state3 = 3'b011, state4 = 3'b100, state5 = 3'b101, state6 = 3'b110, state7 = 3'b111;

reg [7:0] testreg = 0;
reg [6:0] testreg2 = 0;

assign loadscroll_o = scanyy_state == state5 && realx == SCROLLLOAD_X && scanyy == VISIBLEHEIGHT;

always @(posedge clk24) begin
if (scanyy == 0) begin
case (scanyy_state)
Expand Down Expand Up @@ -203,7 +212,7 @@ always @(posedge clk24) begin
scanxx <= scanxx - 1'b1;

// load scroll register at this precise moment
if (scanyy_state == state5 && realx == SCROLLLOAD_X && scanyy == VISIBLEHEIGHT) begin
if (loadscroll_o) begin
fb_row <= {video_scroll_reg, 1'b1};
fb_row_count <= 511;
end
Expand Down Expand Up @@ -246,6 +255,14 @@ reg [9:0] lcd_visible_time = 0;
reg lcd_newline = 0;
assign lcd_newline_o = lcd_newline;

reg vga_hsync_r = 0;
always @(posedge clk24) vga_hsync_r <= hsync;
assign vga_newline_o = vga_hsync_r && ~hsync;

reg tv_hsync_r = 0;
always @(posedge clk24) tv_hsync_r <= tvhs;
assign tv_newline_o = tv_hsync_r && ~tvhs;

always @(posedge clk24)
begin
vsync_r <= vsync;
Expand Down Expand Up @@ -288,23 +305,11 @@ begin

end


// example:
// DE = time >= 63 && time <= 856
// HS = >=11 <11+56


reg lcd_hsync_r = 0;
always @(posedge clk24)
lcd_hsync_r <= ~(lcd_time >= 11 && lcd_time < (11+56)) | ~vsync;
//lcd_hsync_r <= ~(lcd_time >= 15 && lcd_time < (11+56)) | ~vsync;

reg lcd_den_r = 0;
//always @(posedge clk24)
// lcd_den_r = lcd_time >= 76
// && (lcd_time < lcd_visible_time - 55)
// && (sim_lcd_line >= 23) && (sim_lcd_line < 503);

always @(posedge clk24)
lcd_den_r = lcd_time >= (11 + 56)
&& (lcd_time < lcd_visible_time - 9) // 9 shows boot on both, 7 stops working on 7"
Expand All @@ -318,7 +323,8 @@ assign lcd_den_o = lcd_den_r;
assign lcd_den_o = videoActiveY && lcd_active_x;
`endif

assign lcd_y = sim_lcd_line - 23;
assign lcd_y_o = sim_lcd_line - 23;
assign lcd_x_o = lcd_time;

endmodule

Expand Down
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