[docs] minor table format fixing

docs/datasheet/soc.adoc

@@ -79,7 +79,7 @@ clock domain also using registers. However, for ASIC implementations it is recom
 to all inputs and output so the synthesis tool can insert an explicit IO (boundary) scan chain.
 
 .NEORV32 Processor Signal List
-[cols="<3,^1,^1,^1,<8"]
+[cols="<4,^2,^2,^2,<7"]
 [options="header",grid="rows"]
 |=======================
 | Name | Width | Direction | Default | Description