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qei pins
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@burrbull
burrbull committed Apr 17, 2023
1 parent adc4651 commit 0cfbb9a
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Showing 3 changed files with 84 additions and 203 deletions.
2 changes: 1 addition & 1 deletion src/i2c.rs
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Original file line number Diff line number Diff line change
Expand Up @@ -288,7 +288,7 @@ impl<I2C: Instance> I2c<I2C> {
prec: I2C::Rec,
clocks: &CoreClocks,
) -> Self {
let _pins = (pins.0.into(), pins.1.into());
let _pins: (I2C::Scl, I2C::Sda) = (pins.0.into(), pins.1.into());
Self::new_unchecked(i2c, frequency, prec, clocks)
}
/// Create and initialise a new I2C peripheral.
Expand Down
108 changes: 58 additions & 50 deletions src/pwm.rs
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Original file line number Diff line number Diff line change
Expand Up @@ -17,10 +17,10 @@
//! ```rust
//! let gpioa = ..; // Set up and split GPIOA
//! let pins = (
//! gpioa.pa8.into_alternate_af1(),
//! gpioa.pa9.into_alternate_af1(),
//! gpioa.pa10.into_alternate_af1(),
//! gpioa.pa11.into_alternate_af1(),
//! gpioa.pa8.into_alternate(),
//! gpioa.pa9.into_alternate(),
//! gpioa.pa10.into_alternate(),
//! gpioa.pa11.into_alternate(),
//! );
//! ```
//!
Expand Down Expand Up @@ -56,10 +56,10 @@
//! ```rust
//! let gpioa = ..; // Set up and split GPIOA
//! let pins = (
//! gpioa.pa8.into_alternate_af1(),
//! gpioa.pa9.into_alternate_af1(),
//! gpioa.pa10.into_alternate_af1(),
//! gpioa.pa11.into_alternate_af1(),
//! gpioa.pa8.into_alternate(),
//! gpioa.pa9.into_alternate(),
//! gpioa.pa10.into_alternate(),
//! gpioa.pa11.into_alternate(),
//! );
//! ```
//!
Expand Down Expand Up @@ -203,6 +203,10 @@ pub trait FaultPins<TIM> {
const INPUT: BreakInput;
}

pub trait PinCh<const C: u8> {
type Pin;
}

/// Channel wrapper
pub struct Ch<const C: u8>;
impl<const C: u8> Ch<C> {
Expand Down Expand Up @@ -1388,10 +1392,14 @@ pub trait PwmPinEnable {
// Implement PwmPin for timer channels
macro_rules! tim_pin_hal {
// Standard pins (no complementary functionality)
($TIMX:ty, $typ:ty: $(
($CH:ident, $ccmrx_output:ident, $ocxpe:ident, $ocxm:ident),)+
($TIMX:ty, $tim:ident, $typ:ty: $(
($CH:ident, $Ch:ident, $ccmrx_output:ident, $ocxpe:ident, $ocxm:ident),)+
) => {
$(
impl PinCh<$CH> for $TIMX {
type Pin = gpio::alt::$tim::$Ch;
}

impl<COMP> hal::PwmPin for Pwm<$TIMX, $CH, COMP>
where Pwm<$TIMX, $CH, COMP>: PwmPinEnable {
type Duty = $typ;
Expand Down Expand Up @@ -1561,73 +1569,73 @@ macro_rules! tim_pin_hal {

// Dual channel timers
tim_pin_hal! {
pac::TIM12, u16:
(C1, ccmr1_output, oc1pe, oc1m),
(C2, ccmr1_output, oc2pe, oc2m),
pac::TIM12, tim12, u16:
(C1, Ch1, ccmr1_output, oc1pe, oc1m),
(C2, Ch2, ccmr1_output, oc2pe, oc2m),
}
tim_pin_hal! {
pac::TIM15, u16:
(C1, ccmr1_output, oc1pe, oc1m),
(C2, ccmr1_output, oc2pe, oc2m),
pac::TIM15, tim15, u16:
(C1, Ch1, ccmr1_output, oc1pe, oc1m),
(C2, Ch2, ccmr1_output, oc2pe, oc2m),
}

// Single channel timers
tim_pin_hal! {
pac::TIM13, u16: (C1, ccmr1_output, oc1pe, oc1m),
pac::TIM13, tim13, u16: (C1, Ch1, ccmr1_output, oc1pe, oc1m),
}
tim_pin_hal! {
pac::TIM14, u16: (C1, ccmr1_output, oc1pe, oc1m),
pac::TIM14, tim14, u16: (C1, Ch1, ccmr1_output, oc1pe, oc1m),
}
tim_pin_hal! {
pac::TIM16, u16: (C1, ccmr1_output, oc1pe, oc1m),
pac::TIM16, tim16, u16: (C1, Ch1, ccmr1_output, oc1pe, oc1m),
}
tim_pin_hal! {
pac::TIM17, u16: (C1, ccmr1_output, oc1pe, oc1m),
pac::TIM17, tim17, u16: (C1, Ch1, ccmr1_output, oc1pe, oc1m),
}

// Quad channel timers
tim_pin_hal! {
pac::TIM1, u16:
(C1, ccmr1_output, oc1pe, oc1m),
(C2, ccmr1_output, oc2pe, oc2m),
(C3, ccmr2_output, oc3pe, oc3m),
(C4, ccmr2_output, oc4pe, oc4m),
pac::TIM1, tim1, u16:
(C1, Ch1, ccmr1_output, oc1pe, oc1m),
(C2, Ch2, ccmr1_output, oc2pe, oc2m),
(C3, Ch3, ccmr2_output, oc3pe, oc3m),
(C4, Ch4, ccmr2_output, oc4pe, oc4m),
}
tim_pin_hal! {
pac::TIM2, u32:
(C1, ccmr1_output, oc1pe, oc1m),
(C2, ccmr1_output, oc2pe, oc2m),
(C3, ccmr2_output, oc3pe, oc3m),
(C4, ccmr2_output, oc4pe, oc4m),
pac::TIM2, tim2, u32:
(C1, Ch1, ccmr1_output, oc1pe, oc1m),
(C2, Ch2, ccmr1_output, oc2pe, oc2m),
(C3, Ch3, ccmr2_output, oc3pe, oc3m),
(C4, Ch4, ccmr2_output, oc4pe, oc4m),
}
tim_pin_hal! {
pac::TIM3, u16:
(C1, ccmr1_output, oc1pe, oc1m),
(C2, ccmr1_output, oc2pe, oc2m),
(C3, ccmr2_output, oc3pe, oc3m),
(C4, ccmr2_output, oc4pe, oc4m),
pac::TIM3, tim3, u16:
(C1, Ch1, ccmr1_output, oc1pe, oc1m),
(C2, Ch2, ccmr1_output, oc2pe, oc2m),
(C3, Ch3, ccmr2_output, oc3pe, oc3m),
(C4, Ch4, ccmr2_output, oc4pe, oc4m),
}
tim_pin_hal! {
pac::TIM4, u16:
(C1, ccmr1_output, oc1pe, oc1m),
(C2, ccmr1_output, oc2pe, oc2m),
(C3, ccmr2_output, oc3pe, oc3m),
(C4, ccmr2_output, oc4pe, oc4m),
pac::TIM4, tim4, u16:
(C1, Ch1, ccmr1_output, oc1pe, oc1m),
(C2, Ch2, ccmr1_output, oc2pe, oc2m),
(C3, Ch3, ccmr2_output, oc3pe, oc3m),
(C4, Ch4, ccmr2_output, oc4pe, oc4m),
}
tim_pin_hal! {
pac::TIM5, u32:
(C1, ccmr1_output, oc1pe, oc1m),
(C2, ccmr1_output, oc2pe, oc2m),
(C3, ccmr2_output, oc3pe, oc3m),
(C4, ccmr2_output, oc4pe, oc4m),
pac::TIM5, tim5, u32:
(C1, Ch1, ccmr1_output, oc1pe, oc1m),
(C2, Ch2, ccmr1_output, oc2pe, oc2m),
(C3, Ch3, ccmr2_output, oc3pe, oc3m),
(C4, Ch4, ccmr2_output, oc4pe, oc4m),
}
// Quad channel timers
tim_pin_hal! {
pac::TIM8, u16:
(C1, ccmr1_output, oc1pe, oc1m),
(C2, ccmr1_output, oc2pe, oc2m),
(C3, ccmr2_output, oc3pe, oc3m),
(C4, ccmr2_output, oc4pe, oc4m),
pac::TIM8, tim8, u16:
(C1, Ch1, ccmr1_output, oc1pe, oc1m),
(C2, Ch2, ccmr1_output, oc2pe, oc2m),
(C3, Ch3, ccmr2_output, oc3pe, oc3m),
(C4, Ch4, ccmr2_output, oc4pe, oc4m),
}

// Low-power timers
Expand Down
177 changes: 25 additions & 152 deletions src/qei.rs
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Original file line number Diff line number Diff line change
@@ -1,158 +1,35 @@
//! # Quadrature Encoder Interface
use crate::hal::{self, Direction};
use crate::pac;
use crate::pwm::{PinCh, C1, C2};
use crate::rcc::{rec, ResetEnable};

use crate::gpio::{self, Alternate};

use crate::stm32::{TIM1, TIM8};

use crate::stm32::{TIM2, TIM3, TIM4, TIM5};

pub trait Pins<TIM> {}
pub trait PinCh1<TIM> {}
pub trait PinCh2<TIM> {}

impl<TIM, PCH1, PCH2> Pins<TIM> for (PCH1, PCH2)
where
PCH1: PinCh1<TIM>,
PCH2: PinCh2<TIM>,
{
}

macro_rules! pins {
($($TIMX:ty:
CH1: [$($( #[ $pmeta1:meta ] )* $CH1:ty),*]
CH2: [$($( #[ $pmeta2:meta ] )* $CH2:ty),*])+) => {
$(
$(
$( #[ $pmeta1 ] )*
impl PinCh1<$TIMX> for $CH1 {}
)*
$(
$( #[ $pmeta2 ] )*
impl PinCh2<$TIMX> for $CH2 {}
)*
)+
}
}

pins! {
TIM1:
CH1: [
gpio::PA7<Alternate<1>>,
gpio::PA8<Alternate<1>>,
gpio::PB13<Alternate<1>>,
gpio::PE8<Alternate<1>>,
gpio::PE9<Alternate<1>>,
#[cfg(not(feature = "stm32h7b0"))]
gpio::PK0<Alternate<1>>,
#[cfg(not(feature = "stm32h7b0"))]
gpio::PK1<Alternate<1>>
]
CH2: [
gpio::PA9<Alternate<1>>,
gpio::PB0<Alternate<1>>,
gpio::PB14<Alternate<1>>,
gpio::PE10<Alternate<1>>,
gpio::PE11<Alternate<1>>,
#[cfg(not(feature = "stm32h7b0"))]
gpio::PJ10<Alternate<1>>,
#[cfg(not(feature = "stm32h7b0"))]
gpio::PJ11<Alternate<1>>
]

TIM2:
CH1: [
gpio::PA0<Alternate<1>>,
gpio::PA5<Alternate<1>>,
gpio::PA15<Alternate<1>>
]
CH2: [
gpio::PA1<Alternate<1>>,
gpio::PB3<Alternate<1>>
]

TIM3:
CH1: [
gpio::PA6<Alternate<2>>,
gpio::PB4<Alternate<2>>,
gpio::PC6<Alternate<2>>
]
CH2: [
gpio::PA7<Alternate<2>>,
gpio::PB5<Alternate<2>>,
gpio::PC7<Alternate<2>>
]

TIM4:
CH1: [
gpio::PB6<Alternate<2>>,
gpio::PD12<Alternate<2>>
]
CH2: [
gpio::PB7<Alternate<2>>,
gpio::PD13<Alternate<2>>
]

TIM5:
CH1: [
gpio::PA0<Alternate<2>>,
gpio::PH10<Alternate<2>>
]
CH2: [
gpio::PA1<Alternate<2>>,
gpio::PH11<Alternate<2>>
]

TIM8:
CH1: [
gpio::PA5<Alternate<3>>,
gpio::PA7<Alternate<3>>,
gpio::PC6<Alternate<3>>,
gpio::PH13<Alternate<3>>,
#[cfg(not(feature = "rm0468"))]
gpio::PI5<Alternate<3>>,
#[cfg(not(feature = "stm32h7b0"))]
gpio::PJ8<Alternate<3>>,
#[cfg(not(feature = "stm32h7b0"))]
gpio::PJ9<Alternate<3>>
]
CH2: [
gpio::PB0<Alternate<3>>,
gpio::PB14<Alternate<3>>,
gpio::PC7<Alternate<3>>,
gpio::PH14<Alternate<3>>,
#[cfg(not(feature = "rm0468"))]
gpio::PI6<Alternate<3>>,
#[cfg(not(any(feature = "stm32h7b0", feature = "rm0468")))]
gpio::PJ6<Alternate<3>>,
#[cfg(not(feature = "stm32h7b0"))]
gpio::PJ7<Alternate<3>>,
#[cfg(not(feature = "stm32h7b0"))]
gpio::PJ10<Alternate<3>>,
#[cfg(not(feature = "stm32h7b0"))]
gpio::PJ11<Alternate<3>>
]

}

/// Hardware quadrature encoder interface peripheral
pub struct Qei<TIM> {
tim: TIM,
}

pub trait QeiExt<TIM> {
pub trait QeiExt: Sized + PinCh<C1> + PinCh<C2> {
type Rec: ResetEnable;

fn qei<PINS>(self, _pins: PINS, prec: Self::Rec) -> Qei<TIM>
where
PINS: Pins<TIM>;
fn qei(
self,
pins: (
impl Into<<Self as PinCh<C1>>::Pin>,
impl Into<<Self as PinCh<C2>>::Pin>,
),
prec: Self::Rec,
) -> Qei<Self> {
let _pins: (<Self as PinCh<C1>>::Pin, <Self as PinCh<C2>>::Pin) =
(pins.0.into(), pins.1.into());
Self::qei_unchecked(self, prec)
}

fn qei_unchecked(self, prec: Self::Rec) -> Qei<TIM>;
fn qei_unchecked(self, prec: Self::Rec) -> Qei<Self>;
}

macro_rules! tim_hal {
($($TIM:ident: ($tim:ident, $Rec:ident, $bits:ident),)+) => {
($($TIM:ty: ($tim:ident, $Rec:ident, $bits:ident),)+) => {
$(
impl Qei<$TIM> {
/// Configures a TIM peripheral as a quadrature
Expand Down Expand Up @@ -198,14 +75,10 @@ macro_rules! tim_hal {
}
}

impl QeiExt<$TIM> for $TIM {
impl QeiExt for $TIM {
type Rec = rec::$Rec;

fn qei<PINS>(self, _pins: PINS, prec: Self::Rec) -> Qei<$TIM> {
Qei::$tim(self, prec)
}

fn qei_unchecked(self, prec: Self::Rec) -> Qei<$TIM> {
fn qei_unchecked(self, prec: Self::Rec) -> Qei<Self> {
Qei::$tim(self, prec)
}
}
Expand All @@ -231,10 +104,10 @@ macro_rules! tim_hal {
}

tim_hal! {
TIM1: (tim1, Tim1, u16),
TIM8: (tim8, Tim8, u16),
TIM2: (tim2, Tim2, u32),
TIM3: (tim3, Tim3, u16),
TIM4: (tim4, Tim4, u16),
TIM5: (tim5, Tim5, u32),
pac::TIM1: (tim1, Tim1, u16),
pac::TIM8: (tim8, Tim8, u16),
pac::TIM2: (tim2, Tim2, u32),
pac::TIM3: (tim3, Tim3, u16),
pac::TIM4: (tim4, Tim4, u16),
pac::TIM5: (tim5, Tim5, u32),
}

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