Better consistency with STM32F4XX-HAL

examples/blinky.rs

@@ -9,12 +9,12 @@ extern crate panic_halt;
 
 use stm32f7xx_hal as hal;
 
-use crate::hal::{device, prelude::*};
+use crate::hal::{pac, prelude::*};
 use cortex_m_rt::entry;
 
 #[entry]
 fn main() -> ! {
-    let p = device::Peripherals::take().unwrap();
+    let p = pac::Peripherals::take().unwrap();
 
     let gpioi = p.GPIOI.split();
     let mut led = gpioi.pi1.into_push_pull_output();

examples/blinky_delay.rs

@@ -8,11 +8,11 @@
 extern crate panic_halt;
 
 use cortex_m_rt::entry;
-use stm32f7xx_hal::{delay::Delay, device, prelude::*};
+use stm32f7xx_hal::{delay::Delay, pac, prelude::*};
 
 #[entry]
 fn main() -> ! {
-    let p = device::Peripherals::take().unwrap();
+    let p = pac::Peripherals::take().unwrap();
     let cp = cortex_m::Peripherals::take().unwrap();
 
     let gpioi = p.GPIOI.split();

examples/flash.rs

@@ -10,13 +10,13 @@ extern crate panic_semihosting;
 use cortex_m_rt::entry;
 use cortex_m_semihosting::hprintln;
 
-use stm32f7xx_hal::{device, flash::Flash};
+use stm32f7xx_hal::{flash::Flash, pac};
 
 const DATA: &[u8] = &[0, 1, 2, 3, 4];
 
 #[entry]
 fn main() -> ! {
-    let p = device::Peripherals::take().unwrap();
+    let p = pac::Peripherals::take().unwrap();
 
     let mut flash = Flash::new(p.FLASH);
 

examples/serial_delay.rs

@@ -14,14 +14,14 @@ use core::fmt::Write;
 use cortex_m_rt::entry;
 use stm32f7xx_hal::{
     delay::Delay,
-    device,
+    pac,
     prelude::*,
     serial::{self, Serial},
 };
 
 #[entry]
 fn main() -> ! {
-    let p = device::Peripherals::take().unwrap();
+    let p = pac::Peripherals::take().unwrap();
     let cp = cortex_m::Peripherals::take().unwrap();
 
     let rcc = p.RCC.constrain();

examples/serial_dma.rs

@@ -16,15 +16,15 @@ use core::pin::Pin;
 use cortex_m::{asm, interrupt};
 use cortex_m_rt::entry;
 use stm32f7xx_hal::{
-    device,
     dma::{self, DMA},
+    pac,
     prelude::*,
     serial::{self, Serial},
 };
 
 #[entry]
 fn main() -> ! {
-    let p = device::Peripherals::take().unwrap();
+    let p = pac::Peripherals::take().unwrap();
 
     let mut rcc = p.RCC.constrain();
 

examples/serial_echo.rs

@@ -13,14 +13,14 @@ use nb::block;
 
 use cortex_m_rt::entry;
 use stm32f7xx_hal::{
-    device,
+    pac,
     prelude::*,
     serial::{self, Serial},
 };
 
 #[entry]
 fn main() -> ! {
-    let p = device::Peripherals::take().unwrap();
+    let p = pac::Peripherals::take().unwrap();
 
     let rcc = p.RCC.constrain();
     let clocks = rcc.cfgr.sysclk(216.mhz()).freeze();

examples/spi.rs

@@ -5,14 +5,14 @@ extern crate panic_semihosting;
 
 use cortex_m_rt::entry;
 use stm32f7xx_hal::{
-    device,
+    pac,
     prelude::*,
     spi::{self, Spi},
 };
 
 #[entry]
 fn main() -> ! {
-    let p = device::Peripherals::take().unwrap();
+    let p = pac::Peripherals::take().unwrap();
 
     let mut rcc = p.RCC.constrain();
 

examples/spi_16.rs

@@ -5,14 +5,14 @@ extern crate panic_semihosting;
 
 use cortex_m_rt::entry;
 use stm32f7xx_hal::{
-    device,
+    pac,
     prelude::*,
     spi::{self, Spi},
 };
 
 #[entry]
 fn main() -> ! {
-    let p = device::Peripherals::take().unwrap();
+    let p = pac::Peripherals::take().unwrap();
 
     let mut rcc = p.RCC.constrain();
 

examples/spi_dma.rs

@@ -8,15 +8,15 @@ use core::pin::Pin;
 use cortex_m::{asm, interrupt};
 use cortex_m_rt::entry;
 use stm32f7xx_hal::{
-    device,
     dma::{self, DMA},
+    pac,
     prelude::*,
     spi::{self, Spi},
 };
 
 #[entry]
 fn main() -> ! {
-    let p = device::Peripherals::take().unwrap();
+    let p = pac::Peripherals::take().unwrap();
 
     let mut rcc = p.RCC.constrain();
 

examples/spi_dma_16.rs

@@ -8,15 +8,15 @@ use core::pin::Pin;
 use cortex_m::{asm, interrupt};
 use cortex_m_rt::entry;
 use stm32f7xx_hal::{
-    device,
     dma::{self, DMA},
+    pac,
     prelude::*,
     spi::{self, Spi},
 };
 
 #[entry]
 fn main() -> ! {
-    let p = device::Peripherals::take().unwrap();
+    let p = pac::Peripherals::take().unwrap();
 
     let mut rcc = p.RCC.constrain();
 

examples/stm32f7disco-screen/main.rs

@@ -15,9 +15,9 @@ use embedded_graphics::{
 };
 
 use stm32f7xx_hal::{
-    device,
     gpio::Speed,
     ltdc::{Layer, PixelFormat},
+    pac,
     prelude::*,
     rcc::{HSEClock, HSEClockMode, Rcc},
 };
@@ -34,7 +34,7 @@ static mut FB_LAYER1: [u16; FB_GRAPHICS_SIZE] = [0; FB_GRAPHICS_SIZE];
 
 #[entry]
 fn main() -> ! {
-    let perif = device::Peripherals::take().unwrap();
+    let perif = pac::Peripherals::take().unwrap();
     let _cp = cortex_m::Peripherals::take().unwrap();
 
     let rcc_hal: Rcc = perif.RCC.constrain();

examples/stm32f7disco-screen/screen.rs

@@ -2,14 +2,14 @@ use embedded_graphics::{
     drawable::Pixel,
     geometry::Size,
     pixelcolor::{Rgb565, RgbColor},
+    primitives,
     style::{PrimitiveStyle, Styled},
     DrawTarget,
-    primitives
 };
 
 use stm32f7xx_hal::{
-    device::{LTDC, DMA2D},
-    ltdc::{DisplayConfig, Layer, DisplayController, SupportedWord, PixelFormat},
+    ltdc::{DisplayConfig, DisplayController, Layer, PixelFormat, SupportedWord},
+    pac::{DMA2D, LTDC},
     rcc::{HSEClock, HSEClockMode},
     time::U32Ext,
 };
@@ -45,9 +45,7 @@ impl<T: 'static + SupportedWord> Stm32F7DiscoDisplay<T> {
             Some(&HSEClock::new(25.mhz(), HSEClockMode::Bypass)),
         );
 
-        Stm32F7DiscoDisplay {
-            controller,
-        }
+        Stm32F7DiscoDisplay { controller }
     }
 }
 
@@ -68,22 +66,36 @@ impl DrawTarget<Rgb565> for Stm32F7DiscoDisplay<u16> {
     }
 
     /// Draw a hardware accelerated (by DMA2D) rectangle
-    fn draw_rectangle(&mut self, item: &Styled<primitives::Rectangle, PrimitiveStyle<Rgb565>>) -> Result<(), Self::Error> {
+    fn draw_rectangle(
+        &mut self,
+        item: &Styled<primitives::Rectangle, PrimitiveStyle<Rgb565>>,
+    ) -> Result<(), Self::Error> {
         if item.style.stroke_color.is_none() {
-            let top_left = (item.primitive.top_left.x as usize, item.primitive.top_left.y as usize);
-            let bottom_right = (item.primitive.bottom_right.x as usize, item.primitive.bottom_right.y as usize);
+            let top_left = (
+                item.primitive.top_left.x as usize,
+                item.primitive.top_left.y as usize,
+            );
+            let bottom_right = (
+                item.primitive.bottom_right.x as usize,
+                item.primitive.bottom_right.y as usize,
+            );
             let color = match item.style.fill_color {
-                Some(c) =>  {
-                    (c.b() as u32 & 0x1F) | ((c.g() as u32 & 0x3F) << 5) | ((c.r() as u32 & 0x1F) << 11)
-                },
-                None => 0u32 
+                Some(c) => {
+                    (c.b() as u32 & 0x1F)
+                        | ((c.g() as u32 & 0x3F) << 5)
+                        | ((c.r() as u32 & 0x1F) << 11)
+                }
+                None => 0u32,
             };
 
             // Note(unsafe) because transfert might not be before an other write
             // to the buffer occurs. However, such Register -> Buffer transfert
             // is so fast that such issue does not occur
             // TODO : use safer DMA api when the embedde-hal DMA traits will be stabilised
-            unsafe {self.controller.draw_rectangle(Layer::L1, top_left, bottom_right, color);}
+            unsafe {
+                self.controller
+                    .draw_rectangle(Layer::L1, top_left, bottom_right, color);
+            }
         } else {
             self.draw_iter(item).unwrap();
         }

examples/timer.rs

@@ -1,7 +1,7 @@
 //! Test the general purpose timers
 
 #![deny(unsafe_code)]
-#![deny(warnings)]
+//#![deny(warnings)]
 #![no_std]
 #![no_main]
 
@@ -13,7 +13,7 @@ use cortex_m_rt::entry;
 use cortex_m_semihosting::hio;
 
 use stm32f7xx_hal::{
-    device, interrupt,
+    interrupt, pac,
     prelude::*,
     timer::{Event, Timer},
 };
@@ -24,13 +24,13 @@ fn main() -> ! {
     writeln!(hstdout, "Starting timer...").unwrap();
 
     let cp = cortex_m::Peripherals::take().unwrap();
-    let dp = device::Peripherals::take().unwrap();
+    let dp = pac::Peripherals::take().unwrap();
 
     let mut rcc = dp.RCC.constrain();
     let clocks = rcc.cfgr.freeze();
 
     let mut nvic = cp.NVIC;
-    nvic.enable(device::Interrupt::TIM2);
+    nvic.enable(pac::Interrupt::TIM2);
     let mut timer = Timer::tim2(dp.TIM2, 1.hz(), clocks, &mut rcc.apb1);
     timer.listen(Event::TimeOut);
 

src/dma.rs

@@ -11,7 +11,7 @@ use core::{
 use as_slice::AsSlice;
 
 use crate::{
-    device::{
+    pac::{
         self,
         dma2::{self, st::cr},
         Interrupt, DMA1, DMA2, NVIC,
@@ -391,50 +391,50 @@ macro_rules! impl_target {
 // victory and leave this problem to someone who actually needs this capability.
 impl_target!(
     // SPI receive
-    spi::Rx<device::SPI1>, DMA2, Stream0, Channel3, DMA2_STREAM0;
+    spi::Rx<pac::SPI1>, DMA2, Stream0, Channel3, DMA2_STREAM0;
     // SPI1 for DMA2, stream 2, channel 3 is unsupported
-    spi::Rx<device::SPI2>, DMA1, Stream3, Channel0, DMA1_STREAM3;
-    spi::Rx<device::SPI3>, DMA1, Stream0, Channel0, DMA1_STREAM0;
+    spi::Rx<pac::SPI2>, DMA1, Stream3, Channel0, DMA1_STREAM3;
+    spi::Rx<pac::SPI3>, DMA1, Stream0, Channel0, DMA1_STREAM0;
     // SPI3 for DMA1, stream 2, channel 0 is unsupported
-    spi::Rx<device::SPI4>, DMA2, Stream0, Channel4, DMA2_STREAM0;
+    spi::Rx<pac::SPI4>, DMA2, Stream0, Channel4, DMA2_STREAM0;
     // SPI4 for DMA2, stream 3, channel 5 is unsupported
-    spi::Rx<device::SPI5>, DMA2, Stream3, Channel2, DMA2_STREAM3;
+    spi::Rx<pac::SPI5>, DMA2, Stream3, Channel2, DMA2_STREAM3;
     // SPI5 for DMA2, stream 5, channel 7 is unsupported
 
     // SPI transmit
-    spi::Tx<device::SPI1>, DMA2, Stream3, Channel3, DMA2_STREAM3;
+    spi::Tx<pac::SPI1>, DMA2, Stream3, Channel3, DMA2_STREAM3;
     // SPI1 for DMA2, stream 5, channel 3 is unsupported
-    spi::Tx<device::SPI2>, DMA1, Stream4, Channel0, DMA1_STREAM4;
-    spi::Tx<device::SPI3>, DMA1, Stream5, Channel0, DMA1_STREAM5;
+    spi::Tx<pac::SPI2>, DMA1, Stream4, Channel0, DMA1_STREAM4;
+    spi::Tx<pac::SPI3>, DMA1, Stream5, Channel0, DMA1_STREAM5;
     // SPI3 for DMA1, stream 7, channel 0 is unsupported
-    spi::Tx<device::SPI4>, DMA2, Stream1, Channel4, DMA2_STREAM1;
+    spi::Tx<pac::SPI4>, DMA2, Stream1, Channel4, DMA2_STREAM1;
     // SPI4 for DMA2, stream 4, channel 5 is unsupported
-    spi::Tx<device::SPI5>, DMA2, Stream4, Channel2, DMA2_STREAM4;
+    spi::Tx<pac::SPI5>, DMA2, Stream4, Channel2, DMA2_STREAM4;
     // SPI5 for DMA2, stream 6, channel 7 is unsupported
 
     // USART receive
-    serial::Rx<device::USART1>, DMA2, Stream2, Channel4, DMA2_STREAM2;
+    serial::Rx<pac::USART1>, DMA2, Stream2, Channel4, DMA2_STREAM2;
     // USART1 for DMA2, stream 5, channel 4 is unsupported
-    serial::Rx<device::USART2>, DMA1, Stream5, Channel4, DMA1_STREAM5;
-    serial::Rx<device::USART3>, DMA1, Stream1, Channel4, DMA1_STREAM1;
-    serial::Rx<device::UART4>, DMA1, Stream2, Channel4, DMA1_STREAM2;
-    serial::Rx<device::UART5>, DMA1, Stream0, Channel4, DMA1_STREAM0;
-    serial::Rx<device::USART6>, DMA2, Stream1, Channel5, DMA2_STREAM1;
+    serial::Rx<pac::USART2>, DMA1, Stream5, Channel4, DMA1_STREAM5;
+    serial::Rx<pac::USART3>, DMA1, Stream1, Channel4, DMA1_STREAM1;
+    serial::Rx<pac::UART4>, DMA1, Stream2, Channel4, DMA1_STREAM2;
+    serial::Rx<pac::UART5>, DMA1, Stream0, Channel4, DMA1_STREAM0;
+    serial::Rx<pac::USART6>, DMA2, Stream1, Channel5, DMA2_STREAM1;
     // USART6 for DMA2, stream 2, channel 5 is unsupported
-    serial::Rx<device::UART7>, DMA1, Stream3, Channel5, DMA1_STREAM3;
-    serial::Rx<device::UART8>, DMA1, Stream6, Channel5, DMA1_STREAM6;
+    serial::Rx<pac::UART7>, DMA1, Stream3, Channel5, DMA1_STREAM3;
+    serial::Rx<pac::UART8>, DMA1, Stream6, Channel5, DMA1_STREAM6;
 
     // USART transmit
-    serial::Tx<device::USART1>, DMA2, Stream7, Channel4, DMA2_STREAM7;
-    serial::Tx<device::USART2>, DMA1, Stream6, Channel4, DMA1_STREAM6;
-    serial::Tx<device::USART3>, DMA1, Stream3, Channel4, DMA1_STREAM3;
+    serial::Tx<pac::USART1>, DMA2, Stream7, Channel4, DMA2_STREAM7;
+    serial::Tx<pac::USART2>, DMA1, Stream6, Channel4, DMA1_STREAM6;
+    serial::Tx<pac::USART3>, DMA1, Stream3, Channel4, DMA1_STREAM3;
     // USART3 for DMA1, stream 4, channel 7 is unsupported
-    serial::Tx<device::UART4>,  DMA1, Stream4, Channel4, DMA1_STREAM4;
-    serial::Tx<device::UART5>,  DMA1, Stream7, Channel4, DMA1_STREAM7;
-    serial::Tx<device::USART6>, DMA2, Stream6, Channel5, DMA2_STREAM6;
+    serial::Tx<pac::UART4>,  DMA1, Stream4, Channel4, DMA1_STREAM4;
+    serial::Tx<pac::UART5>,  DMA1, Stream7, Channel4, DMA1_STREAM7;
+    serial::Tx<pac::USART6>, DMA2, Stream6, Channel5, DMA2_STREAM6;
     // USART6 for DMA2, stream 7, channel 5 is unsupported
-    serial::Tx<device::UART7>,  DMA1, Stream1, Channel5, DMA1_STREAM1;
-    serial::Tx<device::UART8>,  DMA1, Stream0, Channel5, DMA1_STREAM0;
+    serial::Tx<pac::UART7>,  DMA1, Stream1, Channel5, DMA1_STREAM1;
+    serial::Tx<pac::UART8>,  DMA1, Stream0, Channel5, DMA1_STREAM0;
 );
 
 #[cfg(any(
@@ -449,8 +449,8 @@ impl_target!(
     feature = "stm32f779",
 ))]
 impl_target!(
-    spi::Rx<device::SPI6>, DMA2, Stream6, Channel1, DMA2_STREAM6;
-    spi::Tx<device::SPI6>, DMA2, Stream5, Channel1, DMA2_STREAM5;
+    spi::Rx<pac::SPI6>, DMA2, Stream6, Channel1, DMA2_STREAM6;
+    spi::Tx<pac::SPI6>, DMA2, Stream5, Channel1, DMA2_STREAM5;
 );
 
 /// Implemented for all types that represent DMA streams

src/flash.rs

@@ -1,6 +1,6 @@
 //! Flash memory
 
-use crate::device::FLASH;
+use crate::pac::FLASH;
 use nb::block;
 
 /// Base address of flash memory on AXIM interface.