A RISC-V SOC implemented in nmigen targeting the Arty FPGA board.
Disclaimer: in it's current state, this repo is merely a playground for my learning journey. I am not an expert (read: PR/issues are welcome).
Setup instructions are here
Check SRCS_FIRMWARE in the Makefile, default should run an SDRAM test. Use sim or arty/prog targets.
- single-cycle, runs at 33MHz
- verified with riscv-formal
- serial console (output-only)
- runs from distributed RAM, block RAM, SDRAM
- cache
- GPU: basic VGA is in with a "racing the beam" 1920x1080@60Hz demo screen if you have a Pmod VGA.
- exploring interconnect and limitations about memory ports vs latency: toysoc
Dhrystone -O3:
From distributed RAM:
Number_Of_Runs: 100
User_Time: 39131 cycles, 39129 insn
Cycles_Per_Instruction: 1.000
Dhrystones_Per_Second_Per_MHz: 2555
DMIPS_Per_MHz: 1.454
From block RAM:
Number_Of_Runs: 100
User_Time: 85866 cycles, 36129 insn
Cycles_Per_Instruction: 2.376
Dhrystones_Per_Second_Per_MHz: 1164
DMIPS_Per_MHz: 0.662
From SDRAM (hart clocked @6.25MHz):
Number_Of_Runs: 100
User_Time: 238795 cycles, 39129 insn
Cycles_Per_Instruction: 6.102
Dhrystones_Per_Second_Per_MHz: 418
DMIPS_Per_MHz: 0.237
From SDRAM (hart clocked @33.33MHz):
Number_Of_Runs: 100
User_Time: 613987 cycles, 39129 insn
Cycles_Per_Instruction: 15.691
Dhrystones_Per_Second_Per_MHz: 162
DMIPS_Per_MHz: 0.092