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Added predefined auto trigger number before start. #33

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merged 1 commit into from
Jul 28, 2023
Merged

Added predefined auto trigger number before start. #33

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1 change: 1 addition & 0 deletions python/epix_hr_core/_TriggerRegisters.py
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Original file line number Diff line number Diff line change
Expand Up @@ -37,6 +37,7 @@ def __init__(self, triggerFreq = 1e8, **kwargs):
self.add(pr.RemoteVariable(name='AutoTrigPeriod', description='AutoTrigPeriod', offset=0x00000018, bitSize=32, bitOffset=0, base=pr.UInt, disp = '{}', mode='RW'))
self.add(pr.RemoteVariable(name='PgpTrigEn', description='PgpTrigEn', offset=0x0000001C, bitSize=1, bitOffset=0, base=pr.Bool, mode='RW'))
self.add(pr.RemoteVariable(name='AcqCount', description='AcqCount', offset=0x00000024, bitSize=32, bitOffset=0, base=pr.UInt, disp = '{}', mode='RO'))
self.add(pr.RemoteVariable(name='numberTrigger', description='numberTrigger', offset=0x00000028, bitSize=32, bitOffset=0, base=pr.UInt, disp = '{}', mode='RW'))


#####################################
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12 changes: 11 additions & 1 deletion shared/rtl/AutoTrigger.vhd
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Expand Up @@ -38,6 +38,9 @@ entity AutoTrigger is
-- Number of clock cycles between triggers
trigPeriod : in slv(31 downto 0);

-- Number of triggers
numTriggers : in slv(31 downto 0) := (others => '0');

--Enable run and daq triggers
runEn : in sl;
daqEn : in sl;
Expand All @@ -55,6 +58,7 @@ architecture AutoTrigger of AutoTrigger is
signal timeoutTarget : unsigned(31 downto 0);
signal trigTarget : unsigned(31 downto 0);
signal timeoutCnt : unsigned(31 downto 0) := (others => '0');
signal triggerCnt : unsigned(31 downto 0) := (others => '0');
signal iRunTrigOut : sl := '0';
signal iDaqTrigOut : sl := '0';
-- MUX select types
Expand All @@ -77,6 +81,7 @@ begin
if (sysClkRst = '1') then
iRunTrigOut <= '0' after tpd;
timeoutCnt <= (others => '0') after tpd;
triggerCnt <= (others => '0') after tpd;
else
-- Default output
iRunTrigOut <= '0' after tpd;
Expand All @@ -103,11 +108,16 @@ begin
when INTERNAL_T =>
if (timeoutCnt >= trigTarget) then
timeoutCnt <= (others => '0') after tpd;
iRunTrigOut <= '1' after tpd;
if ((unsigned(numTriggers) = 0) or (triggerCnt < unsigned(numTriggers))) then
iRunTrigOut <= '1' after tpd;
triggerCnt <= triggerCnt + 1 after tpd;
end if;
end if;
end case;
end if;
else
--Reset trigger count
triggerCnt <= (others => '0') after tpd;
--If autotriggers are off, select external triggers
trigSel <= EXTERNAL_T;
end if;
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8 changes: 8 additions & 0 deletions shared/rtl/TrigControlAxi.vhd
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Expand Up @@ -4,6 +4,9 @@
-------------------------------------------------------------------------------
-- Description:
-------------------------------------------------------------------------------
-- History : 2023/7/27 Added the generation of a designated
-- number of triggers by Dawood
-------------------------------------------------------------------------------
-- This file is part of 'EPIX HR Firmware'.
-- It is subject to the license terms in the LICENSE.txt file found in the
-- top-level directory of this distribution and at:
Expand Down Expand Up @@ -80,6 +83,7 @@ architecture rtl of TrigControlAxi is
timingRunEn : sl;
timingDaqEn : sl;
acqCountReset : sl;
numTriggers : slv(31 downto 0);
runTriggerDelay : slv(31 downto 0);
daqTriggerDelay : slv(31 downto 0);
autoTrigPeriod : slv(31 downto 0);
Expand All @@ -94,6 +98,7 @@ architecture rtl of TrigControlAxi is
timingRunEn => '0',
timingDaqEn => '0',
acqCountReset => '0',
numTriggers => (others=>'0'),
runTriggerDelay => (others=>'0'),
daqTriggerDelay => (others=>'0'),
autoTrigPeriod => (others=>'0')
Expand Down Expand Up @@ -357,6 +362,8 @@ begin
daqTrigIn => hwDaqTrig,
-- Number of clock cycles between triggers
trigPeriod => trigSync.autoTrigPeriod,
-- Number of triggers
numTriggers => trigSync.numTriggers,
--Enable run and daq triggers
runEn => autoRunEn,
daqEn => autoDaqEn,
Expand Down Expand Up @@ -415,6 +422,7 @@ begin
axiSlaveRegister (regCon, x"1C", 0, v.trig.pgpTrigEn);
axiSlaveRegister (regCon, x"20", 0, v.trig.acqCountReset);
axiSlaveRegisterR(regCon, x"24", 0, acqCountSync);
axiSlaveRegister (regCon, x"28", 0, v.trig.numTriggers);

axiSlaveDefault(regCon, v.sAxilWriteSlave, v.sAxilReadSlave, AXIL_ERR_RESP_G);

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