Skip to content

Commit

Permalink
Merge remote-tracking branch 'remotes/legoater/tags/pull-aspeed-20210…
Browse files Browse the repository at this point in the history 
…309' into staging

Aspeed patches :

* New model for the Aspeed LPC controller
* Misc cleanups

# gpg: Signature made Tue 09 Mar 2021 11:54:25 GMT
# gpg:                using RSA key A0F66548F04895EBFE6B0B6051A343C7CFFBECA1
# gpg: Good signature from "Cédric Le Goater <[email protected]>" [undefined]
# gpg: WARNING: This key is not certified with a trusted signature!
# gpg:          There is no indication that the signature belongs to the owner.
# Primary key fingerprint: A0F6 6548 F048 95EB FE6B  0B60 51A3 43C7 CFFB ECA1

* remotes/legoater/tags/pull-aspeed-20210309:
  hw/misc: Model KCS devices in the Aspeed LPC controller
  hw/misc: Add a basic Aspeed LPC controller model
  hw/arm: ast2600: Correct the iBT interrupt ID
  hw/arm: ast2600: Set AST2600_MAX_IRQ to value from datasheet
  hw/arm: ast2600: Force a multiple of 32 of IRQs for the GIC
  hw/arm/aspeed: Fix location of firmware images in documentation
  arm/ast2600: Fix SMP booting with -kernel

Signed-off-by: Peter Maydell <[email protected]>
  • Loading branch information
@pm215
pm215 committed Mar 11, 2021
2 parents d689eca + c59f781 commit 363fc96
Show file tree
Hide file tree
Showing 7 changed files with 625 additions and 19 deletions.
16 changes: 10 additions & 6 deletions docs/system/arm/aspeed.rst
View file
Original file line number Diff line number Diff line change
Expand Up @@ -48,6 +48,7 @@ Supported devices
* UART
* Ethernet controllers
* Front LEDs (PCA9552 on I2C bus)
* LPC Peripheral Controller (a subset of subdevices are supported)


Missing devices
Expand All @@ -56,7 +57,6 @@ Missing devices
* Coprocessor support
* ADC (out of tree implementation)
* PWM and Fan Controller
* LPC Bus Controller
* Slave GPIO Controller
* Super I/O Controller
* Hash/Crypto Engine
Expand All @@ -72,18 +72,22 @@ Missing devices
Boot options
------------

The Aspeed machines can be started using the -kernel option to load a
Linux kernel or from a firmware image which can be downloaded from the
OpenPOWER jenkins :
The Aspeed machines can be started using the ``-kernel`` option to
load a Linux kernel or from a firmware. Images can be downloaded from
the OpenBMC jenkins :

https://openpower.xyz/
https://jenkins.openbmc.org/job/ci-openbmc/lastSuccessfulBuild/distro=ubuntu,label=docker-builder

or directly from the OpenBMC GitHub release repository :

https://github.com/openbmc/openbmc/releases

The image should be attached as an MTD drive. Run :

.. code-block:: bash
$ qemu-system-arm -M romulus-bmc -nic user \
-drive file=flash-romulus,format=raw,if=mtd -nographic
-drive file=obmc-phosphor-image-romulus.static.mtd,format=raw,if=mtd -nographic
Options specific to Aspeed machines are :

Expand Down
51 changes: 40 additions & 11 deletions hw/arm/aspeed_ast2600.c
View file
Original file line number Diff line number Diff line change
Expand Up @@ -65,7 +65,7 @@ static const hwaddr aspeed_soc_ast2600_memmap[] = {

#define ASPEED_A7MPCORE_ADDR 0x40460000

#define ASPEED_SOC_AST2600_MAX_IRQ 128
#define AST2600_MAX_IRQ 197

/* Shared Peripheral Interrupt values below are offset by -32 from datasheet */
static const int aspeed_soc_ast2600_irqmap[] = {
Expand Down Expand Up @@ -98,13 +98,13 @@ static const int aspeed_soc_ast2600_irqmap[] = {
[ASPEED_DEV_WDT] = 24,
[ASPEED_DEV_PWM] = 44,
[ASPEED_DEV_LPC] = 35,
[ASPEED_DEV_IBT] = 35, /* LPC */
[ASPEED_DEV_IBT] = 143,
[ASPEED_DEV_I2C] = 110, /* 110 -> 125 */
[ASPEED_DEV_ETH1] = 2,
[ASPEED_DEV_ETH2] = 3,
[ASPEED_DEV_ETH3] = 32,
[ASPEED_DEV_ETH4] = 33,

[ASPEED_DEV_KCS] = 138, /* 138 -> 142 */
};

static qemu_irq aspeed_soc_get_irq(AspeedSoCState *s, int ctrl)
Expand Down Expand Up @@ -211,6 +211,8 @@ static void aspeed_soc_ast2600_init(Object *obj)

object_initialize_child(obj, "emmc-controller.sdhci", &s->emmc.slots[0],
TYPE_SYSBUS_SDHCI);

object_initialize_child(obj, "lpc", &s->lpc, TYPE_ASPEED_LPC);
}

/*
Expand Down Expand Up @@ -241,8 +243,6 @@ static void aspeed_soc_ast2600_realize(DeviceState *dev, Error **errp)

/* CPU */
for (i = 0; i < sc->num_cpus; i++) {
object_property_set_int(OBJECT(&s->cpu[i]), "psci-conduit",
QEMU_PSCI_CONDUIT_SMC, &error_abort);
if (sc->num_cpus > 1) {
object_property_set_int(OBJECT(&s->cpu[i]), "reset-cbar",
ASPEED_A7MPCORE_ADDR, &error_abort);
Expand All @@ -253,11 +253,6 @@ static void aspeed_soc_ast2600_realize(DeviceState *dev, Error **errp)
object_property_set_int(OBJECT(&s->cpu[i]), "cntfrq", 1125000000,
&error_abort);

/*
* TODO: the secondary CPUs are started and a boot helper
* is needed when using -kernel
*/

if (!qdev_realize(DEVICE(&s->cpu[i]), NULL, errp)) {
return;
}
Expand All @@ -267,7 +262,7 @@ static void aspeed_soc_ast2600_realize(DeviceState *dev, Error **errp)
object_property_set_int(OBJECT(&s->a7mpcore), "num-cpu", sc->num_cpus,
&error_abort);
object_property_set_int(OBJECT(&s->a7mpcore), "num-irq",
ASPEED_SOC_AST2600_MAX_IRQ + GIC_INTERNAL,
ROUND_UP(AST2600_MAX_IRQ + GIC_INTERNAL, 32),
&error_abort);

sysbus_realize(SYS_BUS_DEVICE(&s->a7mpcore), &error_abort);
Expand Down Expand Up @@ -469,6 +464,40 @@ static void aspeed_soc_ast2600_realize(DeviceState *dev, Error **errp)
sysbus_mmio_map(SYS_BUS_DEVICE(&s->emmc), 0, sc->memmap[ASPEED_DEV_EMMC]);
sysbus_connect_irq(SYS_BUS_DEVICE(&s->emmc), 0,
aspeed_soc_get_irq(s, ASPEED_DEV_EMMC));

/* LPC */
if (!sysbus_realize(SYS_BUS_DEVICE(&s->lpc), errp)) {
return;
}
sysbus_mmio_map(SYS_BUS_DEVICE(&s->lpc), 0, sc->memmap[ASPEED_DEV_LPC]);

/* Connect the LPC IRQ to the GIC. It is otherwise unused. */
sysbus_connect_irq(SYS_BUS_DEVICE(&s->lpc), 0,
aspeed_soc_get_irq(s, ASPEED_DEV_LPC));

/*
* On the AST2600 LPC subdevice IRQs are connected straight to the GIC.
*
* LPC subdevice IRQ sources are offset from 1 because the LPC model caters
* to the AST2400 and AST2500. SoCs before the AST2600 have one LPC IRQ
* shared across the subdevices, and the shared IRQ output to the VIC is at
* offset 0.
*/
sysbus_connect_irq(SYS_BUS_DEVICE(&s->lpc), 1 + aspeed_lpc_kcs_1,
qdev_get_gpio_in(DEVICE(&s->a7mpcore),
sc->irqmap[ASPEED_DEV_KCS] + aspeed_lpc_kcs_1));

sysbus_connect_irq(SYS_BUS_DEVICE(&s->lpc), 1 + aspeed_lpc_kcs_2,
qdev_get_gpio_in(DEVICE(&s->a7mpcore),
sc->irqmap[ASPEED_DEV_KCS] + aspeed_lpc_kcs_2));

sysbus_connect_irq(SYS_BUS_DEVICE(&s->lpc), 1 + aspeed_lpc_kcs_3,
qdev_get_gpio_in(DEVICE(&s->a7mpcore),
sc->irqmap[ASPEED_DEV_KCS] + aspeed_lpc_kcs_3));

sysbus_connect_irq(SYS_BUS_DEVICE(&s->lpc), 1 + aspeed_lpc_kcs_4,
qdev_get_gpio_in(DEVICE(&s->a7mpcore),
sc->irqmap[ASPEED_DEV_KCS] + aspeed_lpc_kcs_4));
}

static void aspeed_soc_ast2600_class_init(ObjectClass *oc, void *data)
Expand Down
34 changes: 33 additions & 1 deletion hw/arm/aspeed_soc.c
View file
Original file line number Diff line number Diff line change
Expand Up @@ -112,7 +112,6 @@ static const int aspeed_soc_ast2400_irqmap[] = {
[ASPEED_DEV_WDT] = 27,
[ASPEED_DEV_PWM] = 28,
[ASPEED_DEV_LPC] = 8,
[ASPEED_DEV_IBT] = 8, /* LPC */
[ASPEED_DEV_I2C] = 12,
[ASPEED_DEV_ETH1] = 2,
[ASPEED_DEV_ETH2] = 3,
Expand Down Expand Up @@ -211,6 +210,8 @@ static void aspeed_soc_init(Object *obj)
object_initialize_child(obj, "sdhci[*]", &s->sdhci.slots[i],
TYPE_SYSBUS_SDHCI);
}

object_initialize_child(obj, "lpc", &s->lpc, TYPE_ASPEED_LPC);
}

static void aspeed_soc_realize(DeviceState *dev, Error **errp)
Expand Down Expand Up @@ -393,6 +394,37 @@ static void aspeed_soc_realize(DeviceState *dev, Error **errp)
sc->memmap[ASPEED_DEV_SDHCI]);
sysbus_connect_irq(SYS_BUS_DEVICE(&s->sdhci), 0,
aspeed_soc_get_irq(s, ASPEED_DEV_SDHCI));

/* LPC */
if (!sysbus_realize(SYS_BUS_DEVICE(&s->lpc), errp)) {
return;
}
sysbus_mmio_map(SYS_BUS_DEVICE(&s->lpc), 0, sc->memmap[ASPEED_DEV_LPC]);

/* Connect the LPC IRQ to the VIC */
sysbus_connect_irq(SYS_BUS_DEVICE(&s->lpc), 0,
aspeed_soc_get_irq(s, ASPEED_DEV_LPC));

/*
* On the AST2400 and AST2500 the one LPC IRQ is shared between all of the
* subdevices. Connect the LPC subdevice IRQs to the LPC controller IRQ (by
* contrast, on the AST2600, the subdevice IRQs are connected straight to
* the GIC).
*
* LPC subdevice IRQ sources are offset from 1 because the shared IRQ output
* to the VIC is at offset 0.
*/
sysbus_connect_irq(SYS_BUS_DEVICE(&s->lpc), 1 + aspeed_lpc_kcs_1,
qdev_get_gpio_in(DEVICE(&s->lpc), aspeed_lpc_kcs_1));

sysbus_connect_irq(SYS_BUS_DEVICE(&s->lpc), 1 + aspeed_lpc_kcs_2,
qdev_get_gpio_in(DEVICE(&s->lpc), aspeed_lpc_kcs_2));

sysbus_connect_irq(SYS_BUS_DEVICE(&s->lpc), 1 + aspeed_lpc_kcs_3,
qdev_get_gpio_in(DEVICE(&s->lpc), aspeed_lpc_kcs_3));

sysbus_connect_irq(SYS_BUS_DEVICE(&s->lpc), 1 + aspeed_lpc_kcs_4,
qdev_get_gpio_in(DEVICE(&s->lpc), aspeed_lpc_kcs_4));
}
static Property aspeed_soc_properties[] = {
DEFINE_PROP_LINK("dram", AspeedSoCState, dram_mr, TYPE_MEMORY_REGION,
Expand Down
Loading

0 comments on commit 363fc96

Please sign in to comment.