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round 1 of fixing linting issues with designs. #106

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Jul 12, 2024
Merged

round 1 of fixing linting issues with designs. #106

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93f866c
round 1 of slang lint
gadfort Jul 12, 2024
2837f89
cleanup gcd lint
gadfort Jul 12, 2024
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2 changes: 2 additions & 0 deletions scgallery/designs/aes/aes.py
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Original file line number Diff line number Diff line change
Expand Up @@ -31,6 +31,8 @@ def setup(target=asap7_demo):
'aes_sbox.v'):
chip.input(os.path.join(src_root, src), package='scgallery-designs')

chip.add('option', 'idir', src_root, package='scgallery-designs')

if not chip.get('option', 'target'):
chip.load_target(target)

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4 changes: 2 additions & 2 deletions scgallery/designs/ariane/src/ariane.sv2v.v
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Original file line number Diff line number Diff line change
Expand Up @@ -51684,7 +51684,7 @@ module instr_scan
output rvc_call_o;
wire [63:0] rvi_imm_o,rvc_imm_o;
wire is_rvc_o,rvi_return_o,rvi_call_o,rvi_branch_o,rvi_jalr_o,rvi_jump_o,
rvc_branch_o,rvc_jump_o,rvc_jr_o,rvc_return_o,rvc_jalr_o,rvc_call_o,N0,N1,rvc_jalr_o,N2,N3,
rvc_branch_o,rvc_jump_o,rvc_jr_o,rvc_return_o,rvc_jalr_o,rvc_call_o,N0,N1,N2,N3,
N4,N5,N6,N7,N8,N9,N10,N11,N12,N13,N14,N15,N16,N17,N18,N19,N20,N21,N22,N23,N24,
N25,N26,N27,N28,N29,N30,N31,N32,N33,N35,N36,N37,N38,N39,N40,N41,N42,N43,N44,N45,
N46,N47,N48,N49,N50,N51,N52,N53,N54,N55,N56,N57,N58,N59,N60,N61,N62,N63,N64,N65,
Expand Down Expand Up @@ -228233,7 +228233,7 @@ module controller
output flush_tlb_o;
output halt_o;
wire set_pc_commit_o,flush_if_o,flush_unissued_instr_o,flush_id_o,flush_ex_o,
flush_icache_o,flush_tlb_o,halt_o,N0,N1,N2,N3,N4,N5,N6,N7,N8,N9,flush_if_o,flush_ex_o,
flush_icache_o,flush_tlb_o,halt_o,N0,N1,N2,N3,N4,N5,N6,N7,N8,N9,
fence_active_d,flush_dcache,N10,N11,N12,N13,N14,N15,N16,N17,N18,N19,N20,N21,N22,
N23,N24,N25,N26,N27,N28,N29,N30,N31,N32;
reg flush_dcache_o,fence_active_q;
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2 changes: 1 addition & 1 deletion scgallery/designs/black_parrot/src/pickled.v
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Original file line number Diff line number Diff line change
Expand Up @@ -86964,7 +86964,7 @@ module bp_cce_gad_num_way_groups_p64_num_lce_p2_lce_assoc_p8_tag_width_p10_harde
wire [5:0] sharers_ways_o;
wire [3:0] sharers_coh_states_o;
wire transfer_flag_o,replacement_flag_o,upgrade_flag_o,invalidate_flag_o,
exclusive_flag_o,N0,N1,N2,N3,N4,exclusive_flag_o,N5,N6,N7,N8,N9,N10,N11,N12,N13,N14,N15,N16,
exclusive_flag_o,N0,N1,N2,N3,N4,N5,N6,N7,N8,N9,N10,N11,N12,N13,N14,N15,N16,
N17,N18,N19,N20,N21,N22,N23,N24,N25,N26,N27,N28,N29,N30,N31,N32,N33,N34,N35,N36,
N37,N38,N39,N40,N41,N42,N43,N44,N45,N46,N47,N48,N49,N50,N51,N52,N53,N54,N55,N56,
N57,N58,N59,hit,N60,N61,N62,N63,N64,N65,N66,N67,N68,N69,N70,N71,N72,N73,N74,N75,
Expand Down
14 changes: 2 additions & 12 deletions scgallery/designs/gcd/src/gcd.v
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Original file line number Diff line number Diff line change
Expand Up @@ -6,7 +6,6 @@
// friendly to OpenROAD tools
//
// dump-vcd: False
// verilator-xinit: zeros
//module GcdUnit
module gcd
(
Expand Down Expand Up @@ -105,7 +104,6 @@ endmodule // GcdUnit
// GcdUnitCtrlRTL_0x4d0fc71ead8d3d9e
//-----------------------------------------------------------------------------
// dump-vcd: False
// verilator-xinit: zeros
module GcdUnitCtrlRTL_0x4d0fc71ead8d3d9e
(
output reg [ 1:0] a_mux_sel,
Expand Down Expand Up @@ -276,6 +274,8 @@ module GcdUnitCtrlRTL_0x4d0fc71ead8d3d9e
// logic for state_outputs()
always @ (*) begin
current_state__1 = state$out;
do_swap = is_a_lt_b;
do_sub = ~is_b_zero;
if ((current_state__1 == STATE_IDLE)) begin
req_rdy = 1;
resp_val = 0;
Expand All @@ -286,8 +286,6 @@ module GcdUnitCtrlRTL_0x4d0fc71ead8d3d9e
end
else begin
if ((current_state__1 == STATE_CALC)) begin
do_swap = is_a_lt_b;
do_sub = ~is_b_zero;
req_rdy = 0;
resp_val = 0;
a_mux_sel = do_swap ? A_MUX_SEL_B : A_MUX_SEL_SUB;
Expand Down Expand Up @@ -325,7 +323,6 @@ endmodule // GcdUnitCtrlRTL_0x4d0fc71ead8d3d9e
// dtype: 2
// reset_value: 0
// dump-vcd: False
// verilator-xinit: zeros
module RegRst_0x9f365fdf6c8998a
(
input wire [ 0:0] clk,
Expand Down Expand Up @@ -365,7 +362,6 @@ endmodule // RegRst_0x9f365fdf6c8998a
// GcdUnitDpathRTL_0x4d0fc71ead8d3d9e
//-----------------------------------------------------------------------------
// dump-vcd: False
// verilator-xinit: zeros
module GcdUnitDpathRTL_0x4d0fc71ead8d3d9e
(
input wire [ 1:0] a_mux_sel,
Expand Down Expand Up @@ -548,7 +544,6 @@ endmodule // GcdUnitDpathRTL_0x4d0fc71ead8d3d9e
//-----------------------------------------------------------------------------
// dtype: 16
// dump-vcd: False
// verilator-xinit: zeros
module RegEn_0x68db79c4ec1d6e5b
(
input wire [ 0:0] clk,
Expand Down Expand Up @@ -584,7 +579,6 @@ endmodule // RegEn_0x68db79c4ec1d6e5b
//-----------------------------------------------------------------------------
// nbits: 16
// dump-vcd: False
// verilator-xinit: zeros
module LtComparator_0x422b1f52edd46a85
(
input wire [ 0:0] clk,
Expand Down Expand Up @@ -615,7 +609,6 @@ endmodule // LtComparator_0x422b1f52edd46a85
//-----------------------------------------------------------------------------
// nbits: 16
// dump-vcd: False
// verilator-xinit: zeros
module ZeroComparator_0x422b1f52edd46a85
(
input wire [ 0:0] clk,
Expand Down Expand Up @@ -646,7 +639,6 @@ endmodule // ZeroComparator_0x422b1f52edd46a85
// dtype: 16
// nports: 3
// dump-vcd: False
// verilator-xinit: zeros
module Mux_0x683fa1a418b072c9
(
input wire [ 0:0] clk,
Expand Down Expand Up @@ -689,7 +681,6 @@ endmodule // Mux_0x683fa1a418b072c9
// dtype: 16
// nports: 2
// dump-vcd: False
// verilator-xinit: zeros
module Mux_0xdd6473406d1a99a
(
input wire [ 0:0] clk,
Expand Down Expand Up @@ -729,7 +720,6 @@ endmodule // Mux_0xdd6473406d1a99a
//-----------------------------------------------------------------------------
// nbits: 16
// dump-vcd: False
// verilator-xinit: zeros
module Subtractor_0x422b1f52edd46a85
(
input wire [ 0:0] clk,
Expand Down
9 changes: 3 additions & 6 deletions scgallery/designs/ibex/ibex.py
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Original file line number Diff line number Diff line change
Expand Up @@ -44,12 +44,9 @@ def setup(target=asap7_demo):
'ibex_csr.sv',
'ibex_wb_stage.sv',):
chip.input(os.path.join('rtl', src), package='ibex')
for src in ('hw/ip/prim/rtl/prim_assert.sv',):
chip.input(src, package='opentitan')
chip.input('hw/dv/sv/dv_utils/dv_fcov_macros.svh',
fileset='rtl',
filetype='verilog',
package='opentitan')

chip.add('option', 'idir', 'hw/ip/prim/rtl', package='opentitan')
chip.add('option', 'idir', 'hw/dv/sv/dv_utils', package='opentitan')

chip.add('option', 'define', 'SYNTHESIS')

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10 changes: 5 additions & 5 deletions scgallery/designs/tiny_rocket/extra/lambda.v
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Expand Up @@ -84,7 +84,7 @@ module data_arrays_0_0_ext(
input [5:0] RW0_addr,
input RW0_en,
input RW0_wmode,
input [0:0] RW0_wmask,
input RW0_wmask,
input [31:0] RW0_wdata,
output [31:0] RW0_rdata
);
Expand All @@ -95,10 +95,10 @@ module data_arrays_0_0_ext(
.dout (RW0_rdata ),
.ce (RW0_en ),
.we (RW0_wmode ),
.wmask({ {8{RW0_wmask[3]}}
,{8{RW0_wmask[2]}}
,{8{RW0_wmask[1]}}
,{8{RW0_wmask[0]}}}
.wmask({ {8{RW0_wmask}}
,{8{RW0_wmask}}
,{8{RW0_wmask}}
,{8{RW0_wmask}}}
),
.addr (RW0_addr ),
.din (RW0_wdata )
Expand Down