remove use of obsolete target key

scgallery/designs/aes/aes.py

@@ -19,6 +19,8 @@ def setup(target=asap7_demo):
 
     if __name__ == '__main__':
         Gallery.design_commandline(chip)
+    else:
+        chip.load_target(target)
 
     src_root = os.path.join('aes', 'src')
     sdc_root = os.path.join('aes', 'constraints')
@@ -33,9 +35,6 @@ def setup(target=asap7_demo):
 
     chip.add('option', 'idir', src_root, package='scgallery-designs')
 
-    if not chip.get('option', 'target'):
-        chip.load_target(target)
-
     mainlib = chip.get('asic', 'logiclib')[0]
     chip.input(os.path.join(sdc_root, f'{mainlib}.sdc'), package='scgallery-designs')
 

scgallery/designs/ariane/ariane.py

@@ -19,16 +19,15 @@ def setup(target=freepdk45_demo):
 
     if __name__ == '__main__':
         Gallery.design_commandline(chip)
+    else:
+        chip.load_target(target)
 
     src_root = os.path.join('ariane', 'src')
     sdc_root = os.path.join('ariane', 'constraints')
 
     for src in ('ariane.sv2v.v', 'macros.v'):
         chip.input(os.path.join(src_root, src), package='scgallery-designs')
 
-    if not chip.get('option', 'target'):
-        chip.load_target(target)
-
     mainlib = chip.get('asic', 'logiclib')[0]
     chip.input(os.path.join(sdc_root, f'{mainlib}.sdc'), package='scgallery-designs')
 

scgallery/designs/black_parrot/black_parrot.py

@@ -17,6 +17,8 @@ def setup(target=freepdk45_demo):
 
     if __name__ == '__main__':
         Gallery.design_commandline(chip)
+    else:
+        chip.load_target(target)
 
     src_root = os.path.join('black_parrot', 'src')
     extra_root = os.path.join('black_parrot', 'extra')
@@ -25,9 +27,6 @@ def setup(target=freepdk45_demo):
     for src in ('pickled.v',):
         chip.input(os.path.join(src_root, src), package='scgallery-designs')
 
-    if not chip.get('option', 'target'):
-        chip.load_target(target)
-
     mainlib = chip.get('asic', 'logiclib')[0]
     chip.input(os.path.join(sdc_root, f'{mainlib}.sdc'), package='scgallery-designs')
 

scgallery/designs/caliptra/datavault.py

@@ -19,16 +19,15 @@ def setup(target=freepdk45_demo):
 
     if __name__ == '__main__':
         Gallery.design_commandline(chip)
+    else:
+        chip.load_target(target)
 
     sdc_root = os.path.join('caliptra', 'constraints', 'datavault')
 
     chip.use(datavault)
 
     chip.set('option', 'entrypoint', 'dv')
 
-    if not chip.get('option', 'target'):
-        chip.load_target(target)
-
     mainlib = chip.get('asic', 'logiclib')[0]
     chip.input(os.path.join(sdc_root, f'{mainlib}.sdc'), package='scgallery-designs')
 

scgallery/designs/caliptra/keyvault.py

@@ -19,16 +19,15 @@ def setup(target=freepdk45_demo):
 
     if __name__ == '__main__':
         Gallery.design_commandline(chip)
+    else:
+        chip.load_target(target)
 
     sdc_root = os.path.join('caliptra', 'constraints', 'keyvault')
 
     chip.use(keyvault)
 
     chip.set('option', 'entrypoint', 'kv')
 
-    if not chip.get('option', 'target'):
-        chip.load_target(target)
-
     mainlib = chip.get('asic', 'logiclib')[0]
     chip.input(os.path.join(sdc_root, f'{mainlib}.sdc'), package='scgallery-designs')
 

scgallery/designs/caliptra/sha512.py

@@ -19,16 +19,15 @@ def setup(target=freepdk45_demo):
 
     if __name__ == '__main__':
         Gallery.design_commandline(chip)
+    else:
+        chip.load_target(target)
 
     sdc_root = os.path.join('caliptra', 'constraints', 'sha512')
 
     chip.use(sha512)
 
     chip.set('option', 'entrypoint', 'sha512_ctrl')
 
-    if not chip.get('option', 'target'):
-        chip.load_target(target)
-
     mainlib = chip.get('asic', 'logiclib')[0]
     chip.input(os.path.join(sdc_root, f'{mainlib}.sdc'), package='scgallery-designs')
 

scgallery/designs/dynamic_node/dynamic_node.py

@@ -13,6 +13,8 @@ def setup(target=asap7_demo):
 
     if __name__ == '__main__':
         Gallery.design_commandline(chip)
+    else:
+        chip.load_target(target)
 
     sdc_root = os.path.join('dynamic_node', 'constraints')
 
@@ -23,9 +25,6 @@ def setup(target=asap7_demo):
     chip.input('modules/dynamic_node_2dmesh/NETWORK_2dmesh/dynamic_node_2dmesh.pickle.v',
                package='OPDB')
 
-    if not chip.get('option', 'target'):
-        chip.load_target(target)
-
     mainlib = chip.get('asic', 'logiclib')[0]
     chip.input(os.path.join(sdc_root, f'{mainlib}.sdc'), package='scgallery-designs')
 

scgallery/designs/ethmac/ethmac.py

@@ -13,6 +13,8 @@ def setup(target=asap7_demo):
 
     if __name__ == '__main__':
         Gallery.design_commandline(chip)
+    else:
+        chip.load_target(target)
 
     src_root = os.path.join('ethmac', 'src')
     sdc_root = os.path.join('ethmac', 'constraints')
@@ -47,9 +49,6 @@ def setup(target=asap7_demo):
 
     chip.add('option', 'idir', src_root, package='scgallery-designs')
 
-    if not chip.get('option', 'target'):
-        chip.load_target(target)
-
     _common.add_lambdalib_memory(chip)
     chip.add('option', 'define', 'ETH_VIRTUAL_SILICON_RAM')
     chip.input(os.path.join('ethmac', 'extra', 'lambda.v'), package='scgallery-designs')

scgallery/designs/gcd/gcd.py

@@ -4,6 +4,7 @@
 
 from siliconcompiler import Chip
 from siliconcompiler.targets import asap7_demo
+from siliconcompiler.tools._common.asic import get_mainlib
 from scgallery import Gallery
 
 
@@ -12,17 +13,16 @@ def setup(target=asap7_demo):
 
     if __name__ == '__main__':
         Gallery.design_commandline(chip)
+    else:
+        chip.load_target(target)
 
     src_root = os.path.join('gcd', 'src')
     sdc_root = os.path.join('gcd', 'constraints')
 
     for src in ('gcd.v',):
         chip.input(os.path.join(src_root, src), package='scgallery-designs')
 
-    if not chip.get('option', 'target'):
-        chip.load_target(target)
-
-    mainlib = chip.get('asic', 'logiclib')[0]
+    mainlib = get_mainlib(chip)
     chip.input(os.path.join(sdc_root, f'{mainlib}.sdc'), package='scgallery-designs')
 
     chip.set('tool', 'yosys', 'task', 'syn_asic', 'var', 'strategy', 'AREA3')

scgallery/designs/heartbeat/heartbeat.py

@@ -12,16 +12,15 @@ def setup(target=asap7_demo):
 
     if __name__ == '__main__':
         Gallery.design_commandline(chip)
+    else:
+        chip.load_target(target)
 
     src_root = os.path.join('heartbeat', 'src')
     sdc_root = os.path.join('heartbeat', 'constraints')
 
     for src in ('heartbeat.v',):
         chip.input(os.path.join(src_root, src), package='scgallery-designs')
 
-    if not chip.get('option', 'target'):
-        chip.load_target(target)
-
     mainlib = chip.get('asic', 'logiclib')[0]
     chip.input(os.path.join(sdc_root, f'{mainlib}.sdc'), package='scgallery-designs')
 

scgallery/designs/ibex/ibex.py

@@ -13,6 +13,8 @@ def setup(target=asap7_demo):
 
     if __name__ == '__main__':
         Gallery.design_commandline(chip)
+    else:
+        chip.load_target(target)
 
     sdc_root = os.path.join('ibex', 'constraints')
 
@@ -53,9 +55,6 @@ def setup(target=asap7_demo):
 
     chip.add('option', 'define', 'SYNTHESIS')
 
-    if not chip.get('option', 'target'):
-        chip.load_target(target)
-
     mainlib = chip.get('asic', 'logiclib')[0]
     chip.input(os.path.join(sdc_root, f'{mainlib}.sdc'), package='scgallery-designs')
 

scgallery/designs/jpeg/jpeg.py

@@ -13,6 +13,8 @@ def setup(target=asap7_demo):
 
     if __name__ == '__main__':
         Gallery.design_commandline(chip)
+    else:
+        chip.load_target(target)
 
     src_root = os.path.join('jpeg', 'src')
     sdc_root = os.path.join('jpeg', 'constraints')
@@ -34,9 +36,6 @@ def setup(target=asap7_demo):
                 'zigzag.v'):
         chip.input(os.path.join(src_root, src), package='scgallery-designs')
 
-    if not chip.get('option', 'target'):
-        chip.load_target(target)
-
     mainlib = chip.get('asic', 'logiclib')[0]
     chip.input(os.path.join(sdc_root, f'{mainlib}.sdc'), package='scgallery-designs')
 

scgallery/designs/mock_alu/mock_alu.py

@@ -13,6 +13,8 @@ def setup(target=asap7_demo):
 
     if __name__ == '__main__':
         Gallery.design_commandline(chip)
+    else:
+        chip.load_target(target)
 
     src_root = os.path.join('mock_alu', 'src')
     sdc_root = os.path.join('mock_alu', 'constraints')
@@ -42,9 +44,6 @@ def setup(target=asap7_demo):
     chip.add('tool', 'chisel', 'task', 'convert', 'var', 'argument',
              f'--operations {",".join(operations)}')
 
-    if not chip.get('option', 'target'):
-        chip.load_target(target)
-
     mainlib = chip.get('asic', 'logiclib')[0]
     chip.input(os.path.join(sdc_root, f'{mainlib}.sdc'), package='scgallery-designs')
 

scgallery/designs/openmsp430/openmsp430.py

@@ -13,6 +13,8 @@ def setup(target=skywater130_demo):
 
     if __name__ == '__main__':
         Gallery.design_commandline(chip)
+    else:
+        chip.load_target(target)
 
     src_root = os.path.join('core', 'rtl', 'verilog')
     sdc_root = os.path.join('openmsp430', 'constraints')
@@ -44,9 +46,6 @@ def setup(target=skywater130_demo):
                 'omsp_clock_mux.v'):
         chip.input(os.path.join(src_root, src), package='openmsp430')
 
-    if not chip.get('option', 'target'):
-        chip.load_target(target)
-
     mainlib = chip.get('asic', 'logiclib')[0]
     chip.input(os.path.join(sdc_root, f'{mainlib}.sdc'), package='scgallery-designs')
 

scgallery/designs/picorv32/picorv32.py

@@ -12,6 +12,8 @@ def setup(target=skywater130_demo):
 
     if __name__ == '__main__':
         Gallery.design_commandline(chip)
+    else:
+        chip.load_target(target)
 
     sdc_root = os.path.join('picorv32', 'constraints')
 
@@ -22,9 +24,6 @@ def setup(target=skywater130_demo):
     for src in ('picorv32.v',):
         chip.input(src, package='picorv32')
 
-    if not chip.get('option', 'target'):
-        chip.load_target(target)
-
     mainlib = chip.get('asic', 'logiclib')[0]
     chip.input(os.path.join(sdc_root, f'{mainlib}.sdc'), package='scgallery-designs')
 

scgallery/designs/riscv32i/riscv32i.py

@@ -13,6 +13,8 @@ def setup(target=skywater130_demo):
 
     if __name__ == '__main__':
         Gallery.design_commandline(chip)
+    else:
+        chip.load_target(target)
 
     src_root = os.path.join('riscv32i', 'src')
     sdc_root = os.path.join('riscv32i', 'constraints')
@@ -44,9 +46,6 @@ def setup(target=skywater130_demo):
                 'top.v'):
         chip.input(os.path.join(src_root, src), package='scgallery-designs')
 
-    if not chip.get('option', 'target'):
-        chip.load_target(target)
-
     mainlib = chip.get('asic', 'logiclib')[0]
     chip.input(os.path.join(sdc_root, f'{mainlib}.sdc'), package='scgallery-designs')
 

scgallery/designs/spi/spi.py

@@ -12,16 +12,15 @@ def setup(target=asap7_demo):
 
     if __name__ == '__main__':
         Gallery.design_commandline(chip)
+    else:
+        chip.load_target(target)
 
     src_root = os.path.join('spi', 'src')
     sdc_root = os.path.join('spi', 'constraints')
 
     for src in ('spi.v',):
         chip.input(os.path.join(src_root, src), package='scgallery-designs')
 
-    if not chip.get('option', 'target'):
-        chip.load_target(target)
-
     mainlib = chip.get('asic', 'logiclib')[0]
     chip.input(os.path.join(sdc_root, f'{mainlib}.sdc'), package='scgallery-designs')
 

scgallery/designs/swerv/swerv.py

@@ -12,6 +12,8 @@ def setup(target=asap7_demo):
 
     if __name__ == '__main__':
         Gallery.design_commandline(chip)
+    else:
+        chip.load_target(target)
 
     sdc_root = os.path.join('swerv', 'constraints')
     lint_root = os.path.join('swerv', 'lint')
@@ -75,9 +77,6 @@ def setup(target=asap7_demo):
 
     chip.add('option', 'define', 'PHYSICAL')
 
-    if not chip.get('option', 'target'):
-        chip.load_target(target)
-
     mainlib = chip.get('asic', 'logiclib')[0]
     chip.input(os.path.join(sdc_root, f'{mainlib}.sdc'), package='scgallery-designs')
 

scgallery/designs/tiny_rocket/tiny_rocket.py

@@ -14,6 +14,8 @@ def setup(target=freepdk45_demo):
 
     if __name__ == '__main__':
         Gallery.design_commandline(chip)
+    else:
+        chip.load_target(target)
 
     src_root = os.path.join('tiny_rocket', 'src')
     extra_root = os.path.join('tiny_rocket', 'extra')
@@ -25,9 +27,6 @@ def setup(target=freepdk45_demo):
                 'plusarg_reader.v'):
         chip.input(os.path.join(src_root, src), package='scgallery-designs')
 
-    if not chip.get('option', 'target'):
-        chip.load_target(target)
-
     mainlib = chip.get('asic', 'logiclib')[0]
     chip.input(os.path.join(sdc_root, f'{mainlib}.sdc'), package='scgallery-designs')
 

scgallery/designs/uart/uart.py

@@ -12,6 +12,8 @@ def setup(target=asap7_demo):
 
     if __name__ == '__main__':
         Gallery.design_commandline(chip)
+    else:
+        chip.load_target(target)
 
     src_root = os.path.join('uart', 'src')
     sdc_root = os.path.join('uart', 'constraints')
@@ -22,9 +24,6 @@ def setup(target=asap7_demo):
                 'uart_rx.v'):
         chip.input(os.path.join(src_root, src), package='scgallery-designs')
 
-    if not chip.get('option', 'target'):
-        chip.load_target(target)
-
     mainlib = chip.get('asic', 'logiclib')[0]
     chip.input(os.path.join(sdc_root, f'{mainlib}.sdc'), package='scgallery-designs')