use get_mainlib helper function

scgallery/designs/aes/aes.py

@@ -10,6 +10,7 @@
 
 from siliconcompiler import Chip
 from siliconcompiler.targets import asap7_demo
+from siliconcompiler.tools._common.asic import get_mainlib
 from scgallery import Gallery
 
 
@@ -35,7 +36,7 @@ def setup(target=asap7_demo):
 
     chip.add('option', 'idir', src_root, package='scgallery-designs')
 
-    mainlib = chip.get('asic', 'logiclib')[0]
+    mainlib = get_mainlib(chip)
     chip.input(os.path.join(sdc_root, f'{mainlib}.sdc'), package='scgallery-designs')
 
     if mainlib.startswith('sky130'):

scgallery/designs/ariane/ariane.py

@@ -10,6 +10,7 @@
 
 from siliconcompiler import Chip
 from siliconcompiler.targets import freepdk45_demo
+from siliconcompiler.tools._common.asic import get_mainlib
 from scgallery.designs import _common
 from scgallery import Gallery
 
@@ -28,7 +29,7 @@ def setup(target=freepdk45_demo):
     for src in ('ariane.sv2v.v', 'macros.v'):
         chip.input(os.path.join(src_root, src), package='scgallery-designs')
 
-    mainlib = chip.get('asic', 'logiclib')[0]
+    mainlib = get_mainlib(chip)
     chip.input(os.path.join(sdc_root, f'{mainlib}.sdc'), package='scgallery-designs')
 
     chip.set('tool', 'yosys', 'task', 'syn_asic', 'var', 'flatten', 'false')

scgallery/designs/black_parrot/black_parrot.py

@@ -8,6 +8,7 @@
 
 from siliconcompiler import Chip
 from siliconcompiler.targets import freepdk45_demo
+from siliconcompiler.tools._common.asic import get_mainlib
 from scgallery.designs import _common
 from scgallery import Gallery
 
@@ -27,7 +28,7 @@ def setup(target=freepdk45_demo):
     for src in ('pickled.v',):
         chip.input(os.path.join(src_root, src), package='scgallery-designs')
 
-    mainlib = chip.get('asic', 'logiclib')[0]
+    mainlib = get_mainlib(chip)
     chip.input(os.path.join(sdc_root, f'{mainlib}.sdc'), package='scgallery-designs')
 
     chip.set('option', 'define', 'SYNTHESIS')

scgallery/designs/caliptra/datavault.py

@@ -10,6 +10,7 @@
 
 from siliconcompiler import Chip
 from siliconcompiler.targets import freepdk45_demo
+from siliconcompiler.tools._common.asic import get_mainlib
 from scgallery.designs.caliptra.src import datavault
 from scgallery import Gallery
 
@@ -28,7 +29,7 @@ def setup(target=freepdk45_demo):
 
     chip.set('option', 'entrypoint', 'dv')
 
-    mainlib = chip.get('asic', 'logiclib')[0]
+    mainlib = get_mainlib(chip)
     chip.input(os.path.join(sdc_root, f'{mainlib}.sdc'), package='scgallery-designs')
 
     chip.set('constraint', 'density', 30)

scgallery/designs/caliptra/keyvault.py

@@ -10,6 +10,7 @@
 
 from siliconcompiler import Chip
 from siliconcompiler.targets import freepdk45_demo
+from siliconcompiler.tools._common.asic import get_mainlib
 from scgallery.designs.caliptra.src import keyvault
 from scgallery import Gallery
 
@@ -28,7 +29,7 @@ def setup(target=freepdk45_demo):
 
     chip.set('option', 'entrypoint', 'kv')
 
-    mainlib = chip.get('asic', 'logiclib')[0]
+    mainlib = get_mainlib(chip)
     chip.input(os.path.join(sdc_root, f'{mainlib}.sdc'), package='scgallery-designs')
 
     chip.set('constraint', 'density', 20)

scgallery/designs/caliptra/sha512.py

@@ -10,6 +10,7 @@
 
 from siliconcompiler import Chip
 from siliconcompiler.targets import freepdk45_demo
+from siliconcompiler.tools._common.asic import get_mainlib
 from scgallery.designs.caliptra.src import sha512
 from scgallery import Gallery
 
@@ -28,7 +29,7 @@ def setup(target=freepdk45_demo):
 
     chip.set('option', 'entrypoint', 'sha512_ctrl')
 
-    mainlib = chip.get('asic', 'logiclib')[0]
+    mainlib = get_mainlib(chip)
     chip.input(os.path.join(sdc_root, f'{mainlib}.sdc'), package='scgallery-designs')
 
     chip.set('constraint', 'density', 30)

scgallery/designs/dynamic_node/dynamic_node.py

@@ -4,6 +4,7 @@
 
 from siliconcompiler import Chip
 from siliconcompiler.targets import asap7_demo
+from siliconcompiler.tools._common.asic import get_mainlib
 from scgallery import Gallery
 
 
@@ -25,7 +26,7 @@ def setup(target=asap7_demo):
     chip.input('modules/dynamic_node_2dmesh/NETWORK_2dmesh/dynamic_node_2dmesh.pickle.v',
                package='OPDB')
 
-    mainlib = chip.get('asic', 'logiclib')[0]
+    mainlib = get_mainlib(chip)
     chip.input(os.path.join(sdc_root, f'{mainlib}.sdc'), package='scgallery-designs')
 
     return chip

scgallery/designs/ethmac/ethmac.py

@@ -4,6 +4,7 @@
 
 from siliconcompiler import Chip
 from siliconcompiler.targets import asap7_demo
+from siliconcompiler.tools._common.asic import get_mainlib
 from scgallery.designs import _common
 from scgallery import Gallery
 
@@ -53,7 +54,7 @@ def setup(target=asap7_demo):
     chip.add('option', 'define', 'ETH_VIRTUAL_SILICON_RAM')
     chip.input(os.path.join('ethmac', 'extra', 'lambda.v'), package='scgallery-designs')
 
-    mainlib = chip.get('asic', 'logiclib')[0]
+    mainlib = get_mainlib(chip)
     chip.input(os.path.join(sdc_root, f'{mainlib}.sdc'), package='scgallery-designs')
 
     chip.set('tool', 'openroad', 'task', 'floorplan', 'var', 'rtlmp_enable', 'true')

scgallery/designs/heartbeat/heartbeat.py

@@ -4,6 +4,7 @@
 
 from siliconcompiler import Chip
 from siliconcompiler.targets import asap7_demo
+from siliconcompiler.tools._common.asic import get_mainlib
 from scgallery import Gallery
 
 
@@ -21,7 +22,7 @@ def setup(target=asap7_demo):
     for src in ('heartbeat.v',):
         chip.input(os.path.join(src_root, src), package='scgallery-designs')
 
-    mainlib = chip.get('asic', 'logiclib')[0]
+    mainlib = get_mainlib(chip)
     chip.input(os.path.join(sdc_root, f'{mainlib}.sdc'), package='scgallery-designs')
 
     return chip

scgallery/designs/ibex/ibex.py

@@ -4,6 +4,7 @@
 
 from siliconcompiler import Chip
 from siliconcompiler.targets import asap7_demo
+from siliconcompiler.tools._common.asic import get_mainlib
 from scgallery import Gallery
 
 
@@ -55,7 +56,7 @@ def setup(target=asap7_demo):
 
     chip.add('option', 'define', 'SYNTHESIS')
 
-    mainlib = chip.get('asic', 'logiclib')[0]
+    mainlib = get_mainlib(chip)
     chip.input(os.path.join(sdc_root, f'{mainlib}.sdc'), package='scgallery-designs')
 
     if mainlib.startswith('asap7sc7p5t'):

scgallery/designs/jpeg/jpeg.py

@@ -4,6 +4,7 @@
 
 from siliconcompiler import Chip
 from siliconcompiler.targets import asap7_demo
+from siliconcompiler.tools._common.asic import get_mainlib
 from scgallery import Gallery
 
 
@@ -36,7 +37,7 @@ def setup(target=asap7_demo):
                 'zigzag.v'):
         chip.input(os.path.join(src_root, src), package='scgallery-designs')
 
-    mainlib = chip.get('asic', 'logiclib')[0]
+    mainlib = get_mainlib(chip)
     chip.input(os.path.join(sdc_root, f'{mainlib}.sdc'), package='scgallery-designs')
 
     # Lint setup

scgallery/designs/mock_alu/mock_alu.py

@@ -4,6 +4,7 @@
 
 from siliconcompiler import Chip
 from siliconcompiler.targets import asap7_demo
+from siliconcompiler.tools._common.asic import get_mainlib
 from scgallery import Gallery
 
 
@@ -44,7 +45,7 @@ def setup(target=asap7_demo):
     chip.add('tool', 'chisel', 'task', 'convert', 'var', 'argument',
              f'--operations {",".join(operations)}')
 
-    mainlib = chip.get('asic', 'logiclib')[0]
+    mainlib = get_mainlib(chip)
     chip.input(os.path.join(sdc_root, f'{mainlib}.sdc'), package='scgallery-designs')
 
     chip.add('tool', 'chisel', 'task', 'convert', 'var', 'argument', '--tech none')

scgallery/designs/openmsp430/openmsp430.py

@@ -4,6 +4,7 @@
 
 from siliconcompiler import Chip
 from siliconcompiler.targets import skywater130_demo
+from siliconcompiler.tools._common.asic import get_mainlib
 from scgallery import Gallery
 
 
@@ -46,7 +47,7 @@ def setup(target=skywater130_demo):
                 'omsp_clock_mux.v'):
         chip.input(os.path.join(src_root, src), package='openmsp430')
 
-    mainlib = chip.get('asic', 'logiclib')[0]
+    mainlib = get_mainlib(chip)
     chip.input(os.path.join(sdc_root, f'{mainlib}.sdc'), package='scgallery-designs')
 
     return chip

scgallery/designs/picorv32/picorv32.py

@@ -4,6 +4,7 @@
 
 from siliconcompiler import Chip
 from siliconcompiler.targets import skywater130_demo
+from siliconcompiler.tools._common.asic import get_mainlib
 from scgallery import Gallery
 
 
@@ -24,7 +25,7 @@ def setup(target=skywater130_demo):
     for src in ('picorv32.v',):
         chip.input(src, package='picorv32')
 
-    mainlib = chip.get('asic', 'logiclib')[0]
+    mainlib = get_mainlib(chip)
     chip.input(os.path.join(sdc_root, f'{mainlib}.sdc'), package='scgallery-designs')
 
     return chip

scgallery/designs/riscv32i/riscv32i.py

@@ -4,6 +4,7 @@
 
 from siliconcompiler import Chip
 from siliconcompiler.targets import skywater130_demo
+from siliconcompiler.tools._common.asic import get_mainlib
 from scgallery import Gallery
 
 
@@ -46,7 +47,7 @@ def setup(target=skywater130_demo):
                 'top.v'):
         chip.input(os.path.join(src_root, src), package='scgallery-designs')
 
-    mainlib = chip.get('asic', 'logiclib')[0]
+    mainlib = get_mainlib(chip)
     chip.input(os.path.join(sdc_root, f'{mainlib}.sdc'), package='scgallery-designs')
 
     # Lint setup

scgallery/designs/spi/spi.py

@@ -4,6 +4,7 @@
 
 from siliconcompiler import Chip
 from siliconcompiler.targets import asap7_demo
+from siliconcompiler.tools._common.asic import get_mainlib
 from scgallery import Gallery
 
 
@@ -21,7 +22,7 @@ def setup(target=asap7_demo):
     for src in ('spi.v',):
         chip.input(os.path.join(src_root, src), package='scgallery-designs')
 
-    mainlib = chip.get('asic', 'logiclib')[0]
+    mainlib = get_mainlib(chip)
     chip.input(os.path.join(sdc_root, f'{mainlib}.sdc'), package='scgallery-designs')
 
     return chip

scgallery/designs/swerv/swerv.py

@@ -4,6 +4,7 @@
 
 from siliconcompiler import Chip
 from siliconcompiler.targets import asap7_demo
+from siliconcompiler.tools._common.asic import get_mainlib
 from scgallery import Gallery
 
 
@@ -77,7 +78,7 @@ def setup(target=asap7_demo):
 
     chip.add('option', 'define', 'PHYSICAL')
 
-    mainlib = chip.get('asic', 'logiclib')[0]
+    mainlib = get_mainlib(chip)
     chip.input(os.path.join(sdc_root, f'{mainlib}.sdc'), package='scgallery-designs')
 
     # Lint setup

scgallery/designs/tiny_rocket/tiny_rocket.py

@@ -4,6 +4,7 @@
 
 from siliconcompiler import Chip
 from siliconcompiler.targets import freepdk45_demo
+from siliconcompiler.tools._common.asic import get_mainlib
 from scgallery.designs import _common
 from scgallery import Gallery
 
@@ -27,7 +28,7 @@ def setup(target=freepdk45_demo):
                 'plusarg_reader.v'):
         chip.input(os.path.join(src_root, src), package='scgallery-designs')
 
-    mainlib = chip.get('asic', 'logiclib')[0]
+    mainlib = get_mainlib(chip)
     chip.input(os.path.join(sdc_root, f'{mainlib}.sdc'), package='scgallery-designs')
 
     chip.set('option', 'define', 'SYNTHESIS')

scgallery/designs/uart/uart.py

@@ -4,6 +4,7 @@
 
 from siliconcompiler import Chip
 from siliconcompiler.targets import asap7_demo
+from siliconcompiler.tools._common.asic import get_mainlib
 from scgallery import Gallery
 
 
@@ -24,7 +25,7 @@ def setup(target=asap7_demo):
                 'uart_rx.v'):
         chip.input(os.path.join(src_root, src), package='scgallery-designs')
 
-    mainlib = chip.get('asic', 'logiclib')[0]
+    mainlib = get_mainlib(chip)
     chip.input(os.path.join(sdc_root, f'{mainlib}.sdc'), package='scgallery-designs')
 
     # Lint setup

scgallery/rules.py

@@ -1,5 +1,6 @@
 import argparse
 from siliconcompiler import Chip, SiliconCompilerError
+from siliconcompiler.tools._common.asic import get_mainlib
 import os
 import sys
 import json
@@ -135,7 +136,7 @@ def create_rules(chip):
 def update_rules(chip, method, rules):
     rules["date"] = datetime.now().strftime("%Y/%m/%d %H:%M:%S")
 
-    mainlib = chip.get('asic', 'logiclib')[0]
+    mainlib = get_mainlib(chip)
 
     if mainlib not in rules:
         raise ValueError(f'{mainlib} is missing from rules')