start of using packages

.gitmodules

@@ -1,9 +1,3 @@
 [submodule "scgallery/designs/zerosoc/zerosoc"]
 	path = scgallery/designs/zerosoc/zerosoc
 	url = https://github.com/siliconcompiler/zerosoc.git
-[submodule "scgallery/designs/openmsp430/openmsp430"]
-	path = scgallery/designs/openmsp430/openmsp430
-	url = https://github.com/olgirard/openmsp430.git
-[submodule "scgallery/designs/caliptra/src"]
-	path = scgallery/designs/caliptra/src
-	url = https://github.com/chipsalliance/caliptra-rtl

README.md

@@ -14,10 +14,6 @@ Utilize the same python environment as SiliconCompiler.
 
     # To enable zerosoc
     git submodule update --init scgallery/designs/zerosoc/zerosoc/
-    # To enable microwatt
-    git submodule update --init scgallery/designs/microwatt/microwatt/
-    # To enable caliptra
-    git submodule update --init scgallery/designs/caliptra/src/
 
 # To run a design:
 

scgallery/designs/caliptra/_common.py

@@ -2,15 +2,20 @@
 
 
 def __add_sources(chip, root, files):
+    chip.set('dependency', 'caliptra-rtl', 'path',
+             'git+https://github.com/chipsalliance/caliptra-rtl.git')
+    chip.set('dependency', 'caliptra-rtl', 'name', 'caliptra-rtl')
+    chip.set('dependency', 'caliptra-rtl', 'commitid', '440a21d2ce0173139273cf7261a66f490bc630f6')
+
     for src in files:
         chip.input(os.path.join(root, src),
                    fileset='rtl',
-                   filetype='verilog')
+                   filetype='verilog',
+                   dependency='caliptra-rtl')
 
 
 def add_libs(chip):
-    mod_root = os.path.dirname(__file__)
-    libs_root = os.path.join(mod_root, 'src', 'src', 'libs', 'rtl')
+    libs_root = os.path.join('src', 'libs', 'rtl')
     __add_sources(chip, libs_root, ('caliptra_sva.svh',
                                     'caliptra_macros.svh',
                                     'caliptra_sram.sv',
@@ -25,24 +30,21 @@ def add_libs(chip):
 
 
 def add_caliptra_top_defines(chip):
-    mod_root = os.path.dirname(__file__)
-    integration_root = os.path.join(mod_root, 'src', 'src', 'integration', 'rtl')
+    integration_root = os.path.join('src', 'integration', 'rtl')
     __add_sources(chip, integration_root, ('config_defines.svh',
                                            'caliptra_reg_defines.svh'))
 
 
 def add_datavault(chip):
-    mod_root = os.path.dirname(__file__)
-    datavault_root = os.path.join(mod_root, 'src', 'src', 'datavault', 'rtl')
+    datavault_root = os.path.join('src', 'datavault', 'rtl')
     __add_sources(chip, datavault_root, ('dv_reg_pkg.sv',
                                          'dv_reg.sv',
                                          'dv_defines_pkg.sv',
                                          'dv.sv'))
 
 
 def add_keyvault(chip):
-    mod_root = os.path.dirname(__file__)
-    datavault_root = os.path.join(mod_root, 'src', 'src', 'keyvault', 'rtl')
+    datavault_root = os.path.join('src', 'keyvault', 'rtl')
     __add_sources(chip, datavault_root, ('kv_reg_pkg.sv',
                                          'kv_reg.sv',
                                          'kv_defines_pkg.sv',
@@ -54,8 +56,7 @@ def add_keyvault(chip):
 
 
 def add_pcrvault(chip):
-    mod_root = os.path.dirname(__file__)
-    pcrvault_root = os.path.join(mod_root, 'src', 'src', 'pcrvault', 'rtl')
+    pcrvault_root = os.path.join('src', 'pcrvault', 'rtl')
     __add_sources(chip, pcrvault_root, ('pv_reg_pkg.sv',
                                         'pv_reg.sv',
                                         'pv_defines_pkg.sv',
@@ -65,8 +66,7 @@ def add_pcrvault(chip):
 
 
 def add_sha512(chip):
-    mod_root = os.path.dirname(__file__)
-    sha512_root = os.path.join(mod_root, 'src', 'src', 'sha512', 'rtl')
+    sha512_root = os.path.join('src', 'sha512', 'rtl')
     __add_sources(chip, sha512_root, ('sha512_reg_pkg.sv',
                                       'sha512_params_pkg.sv',
                                       'sha512_ctrl.sv',

scgallery/designs/openmsp430/openmsp430.py

@@ -14,9 +14,13 @@ def setup(target=skywater130_demo):
         chip.create_cmdline(chip.design)
 
     mod_root = os.path.dirname(__file__)
-    src_root = os.path.join(mod_root, 'openmsp430', 'core', 'rtl', 'verilog')
+    src_root = os.path.join('core', 'rtl', 'verilog')
     sdc_root = os.path.join(mod_root, 'constraints')
 
+    chip.set('dependency', 'openmsp430', 'path', 'git+https://github.com/olgirard/openmsp430.git')
+    chip.set('dependency', 'openmsp430', 'name', 'openmsp430')
+    chip.set('dependency', 'openmsp430', 'commitid', '92c883abb4518dbc35b027e6cad5ffef5b2fbb81')
+
     for src in ('openMSP430.v',
                 'omsp_frontend.v',
                 'omsp_execution_unit.v',
@@ -38,7 +42,7 @@ def setup(target=skywater130_demo):
                 'omsp_wakeup_cell.v',
                 'omsp_clock_gate.v',
                 'omsp_clock_mux.v'):
-        chip.input(os.path.join(src_root, src))
+        chip.input(os.path.join(src_root, src), dependency='openmsp430')
 
     if not chip.get('option', 'target'):
         chip.load_target(target)