Merge pull request #90 from siliconcompiler/rename_ram_impl_instances

Fix Verilator Warnings
siliconcompiler · Nov 19, 2024 · fce9df2 · fce9df2
2 parents 29c23dc + 0b7bec5
commit fce9df2
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diff --git a/lambdalib/ramlib/rtl/la_dpram.v b/lambdalib/ramlib/rtl/la_dpram.v
@@ -53,7 +53,7 @@ module la_dpram #(
         .PROP       (PROP),
         .CTRLW      (CTRLW),
         .TESTW      (TESTW)
-    ) ram (
+    ) memory (
         .wr_clk     (wr_clk),
         .wr_ce      (wr_ce),
         .wr_we      (wr_we),

diff --git a/lambdalib/ramlib/rtl/la_spram.v b/lambdalib/ramlib/rtl/la_spram.v
@@ -49,7 +49,7 @@ module la_spram #(
         .PROP   (PROP),
         .CTRLW  (CTRLW),
         .TESTW  (TESTW)
-    ) ram (
+    ) memory (
         .clk    (clk),
         .ce     (ce),
         .we     (we),