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CSR names instead of registers
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Signed-off-by: Kristine Dosvik <[email protected]>
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@silabs-krdosvik
silabs-krdosvik committed Dec 1, 2023
1 parent 38eebfc commit d16440a
Showing 1 changed file with 117 additions and 116 deletions.
233 changes: 117 additions & 116 deletions cv32e40s/tests/programs/custom/mhpmcounter_write_test/mhpmcounter_write_test.c
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Original file line number Diff line number Diff line change
Expand Up @@ -20,140 +20,141 @@
#include <stdint.h>
#include <stdlib.h>


int write_mhpmcounters()
{
uint32_t reg = 0;
__asm__ volatile("mv %0, x0" : "=r"(reg));
__asm__ volatile("not %0, %0" :: "r"(reg));
__asm__ volatile("csrrs x0, 0xB03, %0" :: "r"(reg));
__asm__ volatile("csrrs x0, 0xB04, %0" :: "r"(reg));
__asm__ volatile("csrrs x0, 0xB05, %0" :: "r"(reg));
__asm__ volatile("csrrs x0, 0xB06, %0" :: "r"(reg));
__asm__ volatile("csrrs x0, 0xB07, %0" :: "r"(reg));
__asm__ volatile("csrrs x0, 0xB08, %0" :: "r"(reg));
__asm__ volatile("csrrs x0, 0xB09, %0" :: "r"(reg));
__asm__ volatile("csrrs x0, 0xB0A, %0" :: "r"(reg));
__asm__ volatile("csrrs x0, 0xB0B, %0" :: "r"(reg));
__asm__ volatile("csrrs x0, 0xB0C, %0" :: "r"(reg));
__asm__ volatile("csrrs x0, 0xB0D, %0" :: "r"(reg));
__asm__ volatile("csrrs x0, 0xB0E, %0" :: "r"(reg));
__asm__ volatile("csrrs x0, 0xB0F, %0" :: "r"(reg));
__asm__ volatile("csrrs x0, 0xB10, %0" :: "r"(reg));
__asm__ volatile("csrrs x0, 0xB11, %0" :: "r"(reg));
__asm__ volatile("csrrs x0, 0xB12, %0" :: "r"(reg));
__asm__ volatile("csrrs x0, 0xB13, %0" :: "r"(reg));
__asm__ volatile("csrrs x0, 0xB14, %0" :: "r"(reg));
__asm__ volatile("csrrs x0, 0xB15, %0" :: "r"(reg));
__asm__ volatile("csrrs x0, 0xB16, %0" :: "r"(reg));
__asm__ volatile("csrrs x0, 0xB17, %0" :: "r"(reg));
__asm__ volatile("csrrs x0, 0xB18, %0" :: "r"(reg));
__asm__ volatile("csrrs x0, 0xB19, %0" :: "r"(reg));
__asm__ volatile("csrrs x0, 0xB1A, %0" :: "r"(reg));
__asm__ volatile("csrrs x0, 0xB1B, %0" :: "r"(reg));
__asm__ volatile("csrrs x0, 0xB1C, %0" :: "r"(reg));
__asm__ volatile("csrrs x0, 0xB1D, %0" :: "r"(reg));
__asm__ volatile("csrrs x0, 0xB1E, %0" :: "r"(reg));
__asm__ volatile("csrrs x0, 0xB1F, %0" :: "r"(reg));
__asm__ volatile("csrrs x0, mhpmcounter3, %0" :: "r"(reg));
__asm__ volatile("csrrs x0, mhpmcounter4, %0" :: "r"(reg));
__asm__ volatile("csrrs x0, mhpmcounter5, %0" :: "r"(reg));
__asm__ volatile("csrrs x0, mhpmcounter6, %0" :: "r"(reg));
__asm__ volatile("csrrs x0, mhpmcounter7, %0" :: "r"(reg));
__asm__ volatile("csrrs x0, mhpmcounter8, %0" :: "r"(reg));
__asm__ volatile("csrrs x0, mhpmcounter9, %0" :: "r"(reg));
__asm__ volatile("csrrs x0, mhpmcounter10, %0" :: "r"(reg));
__asm__ volatile("csrrs x0, mhpmcounter11, %0" :: "r"(reg));
__asm__ volatile("csrrs x0, mhpmcounter12, %0" :: "r"(reg));
__asm__ volatile("csrrs x0, mhpmcounter13, %0" :: "r"(reg));
__asm__ volatile("csrrs x0, mhpmcounter14, %0" :: "r"(reg));
__asm__ volatile("csrrs x0, mhpmcounter15, %0" :: "r"(reg));
__asm__ volatile("csrrs x0, mhpmcounter16, %0" :: "r"(reg));
__asm__ volatile("csrrs x0, mhpmcounter17, %0" :: "r"(reg));
__asm__ volatile("csrrs x0, mhpmcounter18, %0" :: "r"(reg));
__asm__ volatile("csrrs x0, mhpmcounter19, %0" :: "r"(reg));
__asm__ volatile("csrrs x0, mhpmcounter20, %0" :: "r"(reg));
__asm__ volatile("csrrs x0, mhpmcounter21, %0" :: "r"(reg));
__asm__ volatile("csrrs x0, mhpmcounter22, %0" :: "r"(reg));
__asm__ volatile("csrrs x0, mhpmcounter23, %0" :: "r"(reg));
__asm__ volatile("csrrs x0, mhpmcounter24, %0" :: "r"(reg));
__asm__ volatile("csrrs x0, mhpmcounter25, %0" :: "r"(reg));
__asm__ volatile("csrrs x0, mhpmcounter26, %0" :: "r"(reg));
__asm__ volatile("csrrs x0, mhpmcounter27, %0" :: "r"(reg));
__asm__ volatile("csrrs x0, mhpmcounter28, %0" :: "r"(reg));
__asm__ volatile("csrrs x0, mhpmcounter29, %0" :: "r"(reg));
__asm__ volatile("csrrs x0, mhpmcounter30, %0" :: "r"(reg));
__asm__ volatile("csrrs x0, mhpmcounter31, %0" :: "r"(reg));

return 0;
}

int write_mhpmcounterhs()
{
uint32_t reg = 0;
__asm__ volatile("csrrs x0, 0xB83, %0" :: "r"(reg));
__asm__ volatile("csrrs x0, 0xB84, %0" :: "r"(reg));
__asm__ volatile("csrrs x0, 0xB85, %0" :: "r"(reg));
__asm__ volatile("csrrs x0, 0xB86, %0" :: "r"(reg));
__asm__ volatile("csrrs x0, 0xB87, %0" :: "r"(reg));
__asm__ volatile("csrrs x0, 0xB88, %0" :: "r"(reg));
__asm__ volatile("csrrs x0, 0xB89, %0" :: "r"(reg));
__asm__ volatile("csrrs x0, 0xB8A, %0" :: "r"(reg));
__asm__ volatile("csrrs x0, 0xB8B, %0" :: "r"(reg));
__asm__ volatile("csrrs x0, 0xB8C, %0" :: "r"(reg));
__asm__ volatile("csrrs x0, 0xB8D, %0" :: "r"(reg));
__asm__ volatile("csrrs x0, 0xB8E, %0" :: "r"(reg));
__asm__ volatile("csrrs x0, 0xB8F, %0" :: "r"(reg));
__asm__ volatile("csrrs x0, 0xB90, %0" :: "r"(reg));
__asm__ volatile("csrrs x0, 0xB91, %0" :: "r"(reg));
__asm__ volatile("csrrs x0, 0xB92, %0" :: "r"(reg));
__asm__ volatile("csrrs x0, 0xB93, %0" :: "r"(reg));
__asm__ volatile("csrrs x0, 0xB94, %0" :: "r"(reg));
__asm__ volatile("csrrs x0, 0xB95, %0" :: "r"(reg));
__asm__ volatile("csrrs x0, 0xB96, %0" :: "r"(reg));
__asm__ volatile("csrrs x0, 0xB97, %0" :: "r"(reg));
__asm__ volatile("csrrs x0, 0xB98, %0" :: "r"(reg));
__asm__ volatile("csrrs x0, 0xB99, %0" :: "r"(reg));
__asm__ volatile("csrrs x0, 0xB9A, %0" :: "r"(reg));
__asm__ volatile("csrrs x0, 0xB9B, %0" :: "r"(reg));
__asm__ volatile("csrrs x0, 0xB9C, %0" :: "r"(reg));
__asm__ volatile("csrrs x0, 0xB9D, %0" :: "r"(reg));
__asm__ volatile("csrrs x0, 0xB9E, %0" :: "r"(reg));
__asm__ volatile("csrrs x0, 0xB9F, %0" :: "r"(reg));
__asm__ volatile("csrrs x0, mhpmcounter3h, %0" :: "r"(reg));
__asm__ volatile("csrrs x0, mhpmcounter4h, %0" :: "r"(reg));
__asm__ volatile("csrrs x0, mhpmcounter5h, %0" :: "r"(reg));
__asm__ volatile("csrrs x0, mhpmcounter6h, %0" :: "r"(reg));
__asm__ volatile("csrrs x0, mhpmcounter7h, %0" :: "r"(reg));
__asm__ volatile("csrrs x0, mhpmcounter8h, %0" :: "r"(reg));
__asm__ volatile("csrrs x0, mhpmcounter9h, %0" :: "r"(reg));
__asm__ volatile("csrrs x0, mhpmcounter10h, %0" :: "r"(reg));
__asm__ volatile("csrrs x0, mhpmcounter11h, %0" :: "r"(reg));
__asm__ volatile("csrrs x0, mhpmcounter12h, %0" :: "r"(reg));
__asm__ volatile("csrrs x0, mhpmcounter13h, %0" :: "r"(reg));
__asm__ volatile("csrrs x0, mhpmcounter14h, %0" :: "r"(reg));
__asm__ volatile("csrrs x0, mhpmcounter15h, %0" :: "r"(reg));
__asm__ volatile("csrrs x0, mhpmcounter16h, %0" :: "r"(reg));
__asm__ volatile("csrrs x0, mhpmcounter17h, %0" :: "r"(reg));
__asm__ volatile("csrrs x0, mhpmcounter18h, %0" :: "r"(reg));
__asm__ volatile("csrrs x0, mhpmcounter19h, %0" :: "r"(reg));
__asm__ volatile("csrrs x0, mhpmcounter20h, %0" :: "r"(reg));
__asm__ volatile("csrrs x0, mhpmcounter21h, %0" :: "r"(reg));
__asm__ volatile("csrrs x0, mhpmcounter22h, %0" :: "r"(reg));
__asm__ volatile("csrrs x0, mhpmcounter23h, %0" :: "r"(reg));
__asm__ volatile("csrrs x0, mhpmcounter24h, %0" :: "r"(reg));
__asm__ volatile("csrrs x0, mhpmcounter25h, %0" :: "r"(reg));
__asm__ volatile("csrrs x0, mhpmcounter26h, %0" :: "r"(reg));
__asm__ volatile("csrrs x0, mhpmcounter27h, %0" :: "r"(reg));
__asm__ volatile("csrrs x0, mhpmcounter28h, %0" :: "r"(reg));
__asm__ volatile("csrrs x0, mhpmcounter29h, %0" :: "r"(reg));
__asm__ volatile("csrrs x0, mhpmcounter30h, %0" :: "r"(reg));
__asm__ volatile("csrrs x0, mhpmcounter31h, %0" :: "r"(reg));

return 0;
}

int check_mhpmcounters_are_zero()
{
uint32_t reg = 0;
__asm__ volatile("csrr %0, 0xB03" : "=r"(reg));
__asm__ volatile("csrr %0, mhpmcounter3" : "=r"(reg));
if(reg != 0) return 1;
__asm__ volatile("csrr %0, 0xB04" : "=r"(reg));
__asm__ volatile("csrr %0, mhpmcounter4" : "=r"(reg));
if(reg != 0) return 1;
__asm__ volatile("csrr %0, 0xB05" : "=r"(reg));
__asm__ volatile("csrr %0, mhpmcounter5" : "=r"(reg));
if(reg != 0) return 1;
__asm__ volatile("csrr %0, 0xB06" : "=r"(reg));
__asm__ volatile("csrr %0, mhpmcounter6" : "=r"(reg));
if(reg != 0) return 1;
__asm__ volatile("csrr %0, 0xB07" : "=r"(reg));
__asm__ volatile("csrr %0, mhpmcounter7" : "=r"(reg));
if(reg != 0) return 1;
__asm__ volatile("csrr %0, 0xB08" : "=r"(reg));
__asm__ volatile("csrr %0, mhpmcounter8" : "=r"(reg));
if(reg != 0) return 1;
__asm__ volatile("csrr %0, 0xB09" : "=r"(reg));
__asm__ volatile("csrr %0, mhpmcounter9" : "=r"(reg));
if(reg != 0) return 1;
__asm__ volatile("csrr %0, 0xB0A" : "=r"(reg));
__asm__ volatile("csrr %0, mhpmcounter10" : "=r"(reg));
if(reg != 0) return 1;
__asm__ volatile("csrr %0, 0xB0B" : "=r"(reg));
__asm__ volatile("csrr %0, mhpmcounter11" : "=r"(reg));
if(reg != 0) return 1;
__asm__ volatile("csrr %0, 0xB0C" : "=r"(reg));
__asm__ volatile("csrr %0, mhpmcounter12" : "=r"(reg));
if(reg != 0) return 1;
__asm__ volatile("csrr %0, 0xB0D" : "=r"(reg));
__asm__ volatile("csrr %0, mhpmcounter13" : "=r"(reg));
if(reg != 0) return 1;
__asm__ volatile("csrr %0, 0xB0E" : "=r"(reg));
__asm__ volatile("csrr %0, mhpmcounter14" : "=r"(reg));
if(reg != 0) return 1;
__asm__ volatile("csrr %0, 0xB0F" : "=r"(reg));
__asm__ volatile("csrr %0, mhpmcounter15" : "=r"(reg));
if(reg != 0) return 1;
__asm__ volatile("csrr %0, 0xB10" : "=r"(reg));
__asm__ volatile("csrr %0, mhpmcounter16" : "=r"(reg));
if(reg != 0) return 1;
__asm__ volatile("csrr %0, 0xB11" : "=r"(reg));
__asm__ volatile("csrr %0, mhpmcounter17" : "=r"(reg));
if(reg != 0) return 1;
__asm__ volatile("csrr %0, 0xB12" : "=r"(reg));
__asm__ volatile("csrr %0, mhpmcounter18" : "=r"(reg));
if(reg != 0) return 1;
__asm__ volatile("csrr %0, 0xB13" : "=r"(reg));
__asm__ volatile("csrr %0, mhpmcounter19" : "=r"(reg));
if(reg != 0) return 1;
__asm__ volatile("csrr %0, 0xB14" : "=r"(reg));
__asm__ volatile("csrr %0, mhpmcounter20" : "=r"(reg));
if(reg != 0) return 1;
__asm__ volatile("csrr %0, 0xB15" : "=r"(reg));
__asm__ volatile("csrr %0, mhpmcounter21" : "=r"(reg));
if(reg != 0) return 1;
__asm__ volatile("csrr %0, 0xB16" : "=r"(reg));
__asm__ volatile("csrr %0, mhpmcounter22" : "=r"(reg));
if(reg != 0) return 1;
__asm__ volatile("csrr %0, 0xB17" : "=r"(reg));
__asm__ volatile("csrr %0, mhpmcounter23" : "=r"(reg));
if(reg != 0) return 1;
__asm__ volatile("csrr %0, 0xB18" : "=r"(reg));
__asm__ volatile("csrr %0, mhpmcounter24" : "=r"(reg));
if(reg != 0) return 1;
__asm__ volatile("csrr %0, 0xB19" : "=r"(reg));
__asm__ volatile("csrr %0, mhpmcounter25" : "=r"(reg));
if(reg != 0) return 1;
__asm__ volatile("csrr %0, 0xB1A" : "=r"(reg));
__asm__ volatile("csrr %0, mhpmcounter26" : "=r"(reg));
if(reg != 0) return 1;
__asm__ volatile("csrr %0, 0xB1B" : "=r"(reg));
__asm__ volatile("csrr %0, mhpmcounter27" : "=r"(reg));
if(reg != 0) return 1;
__asm__ volatile("csrr %0, 0xB1C" : "=r"(reg));
__asm__ volatile("csrr %0, mhpmcounter28" : "=r"(reg));
if(reg != 0) return 1;
__asm__ volatile("csrr %0, 0xB1D" : "=r"(reg));
__asm__ volatile("csrr %0, mhpmcounter29" : "=r"(reg));
if(reg != 0) return 1;
__asm__ volatile("csrr %0, 0xB1E" : "=r"(reg));
__asm__ volatile("csrr %0, mhpmcounter30" : "=r"(reg));
if(reg != 0) return 1;
__asm__ volatile("csrr %0, 0xB1F" : "=r"(reg));
__asm__ volatile("csrr %0, mhpmcounter31" : "=r"(reg));
if(reg != 0) return 1;

return 0;
Expand All @@ -162,63 +163,63 @@ int check_mhpmcounters_are_zero()
int check_mhpmcounterhs_are_zero()
{
uint32_t reg = 0;
__asm__ volatile("csrr %0, 0xB83" : "=r"(reg));
__asm__ volatile("csrr %0, mhpmcounter3h" : "=r"(reg));
if(reg != 0) return 1;
__asm__ volatile("csrr %0, 0xB84" : "=r"(reg));
__asm__ volatile("csrr %0, mhpmcounter4h" : "=r"(reg));
if(reg != 0) return 1;
__asm__ volatile("csrr %0, 0xB85" : "=r"(reg));
__asm__ volatile("csrr %0, mhpmcounter5h" : "=r"(reg));
if(reg != 0) return 1;
__asm__ volatile("csrr %0, 0xB86" : "=r"(reg));
__asm__ volatile("csrr %0, mhpmcounter6h" : "=r"(reg));
if(reg != 0) return 1;
__asm__ volatile("csrr %0, 0xB87" : "=r"(reg));
__asm__ volatile("csrr %0, mhpmcounter7h" : "=r"(reg));
if(reg != 0) return 1;
__asm__ volatile("csrr %0, 0xB88" : "=r"(reg));
__asm__ volatile("csrr %0, mhpmcounter8h" : "=r"(reg));
if(reg != 0) return 1;
__asm__ volatile("csrr %0, 0xB89" : "=r"(reg));
__asm__ volatile("csrr %0, mhpmcounter9h" : "=r"(reg));
if(reg != 0) return 1;
__asm__ volatile("csrr %0, 0xB8A" : "=r"(reg));
__asm__ volatile("csrr %0, mhpmcounter10h" : "=r"(reg));
if(reg != 0) return 1;
__asm__ volatile("csrr %0, 0xB8B" : "=r"(reg));
__asm__ volatile("csrr %0, mhpmcounter11h" : "=r"(reg));
if(reg != 0) return 1;
__asm__ volatile("csrr %0, 0xB8C" : "=r"(reg));
__asm__ volatile("csrr %0, mhpmcounter12h" : "=r"(reg));
if(reg != 0) return 1;
__asm__ volatile("csrr %0, 0xB8D" : "=r"(reg));
__asm__ volatile("csrr %0, mhpmcounter13h" : "=r"(reg));
if(reg != 0) return 1;
__asm__ volatile("csrr %0, 0xB8E" : "=r"(reg));
__asm__ volatile("csrr %0, mhpmcounter14h" : "=r"(reg));
if(reg != 0) return 1;
__asm__ volatile("csrr %0, 0xB8F" : "=r"(reg));
__asm__ volatile("csrr %0, mhpmcounter15h" : "=r"(reg));
if(reg != 0) return 1;
__asm__ volatile("csrr %0, 0xB90" : "=r"(reg));
__asm__ volatile("csrr %0, mhpmcounter16h" : "=r"(reg));
if(reg != 0) return 1;
__asm__ volatile("csrr %0, 0xB91" : "=r"(reg));
__asm__ volatile("csrr %0, mhpmcounter17h" : "=r"(reg));
if(reg != 0) return 1;
__asm__ volatile("csrr %0, 0xB92" : "=r"(reg));
__asm__ volatile("csrr %0, mhpmcounter18h" : "=r"(reg));
if(reg != 0) return 1;
__asm__ volatile("csrr %0, 0xB93" : "=r"(reg));
__asm__ volatile("csrr %0, mhpmcounter19h" : "=r"(reg));
if(reg != 0) return 1;
__asm__ volatile("csrr %0, 0xB94" : "=r"(reg));
__asm__ volatile("csrr %0, mhpmcounter20h" : "=r"(reg));
if(reg != 0) return 1;
__asm__ volatile("csrr %0, 0xB95" : "=r"(reg));
__asm__ volatile("csrr %0, mhpmcounter21h" : "=r"(reg));
if(reg != 0) return 1;
__asm__ volatile("csrr %0, 0xB96" : "=r"(reg));
__asm__ volatile("csrr %0, mhpmcounter22h" : "=r"(reg));
if(reg != 0) return 1;
__asm__ volatile("csrr %0, 0xB97" : "=r"(reg));
__asm__ volatile("csrr %0, mhpmcounter23h" : "=r"(reg));
if(reg != 0) return 1;
__asm__ volatile("csrr %0, 0xB98" : "=r"(reg));
__asm__ volatile("csrr %0, mhpmcounter24h" : "=r"(reg));
if(reg != 0) return 1;
__asm__ volatile("csrr %0, 0xB99" : "=r"(reg));
__asm__ volatile("csrr %0, mhpmcounter25h" : "=r"(reg));
if(reg != 0) return 1;
__asm__ volatile("csrr %0, 0xB9A" : "=r"(reg));
__asm__ volatile("csrr %0, mhpmcounter26h" : "=r"(reg));
if(reg != 0) return 1;
__asm__ volatile("csrr %0, 0xB9B" : "=r"(reg));
__asm__ volatile("csrr %0, mhpmcounter27h" : "=r"(reg));
if(reg != 0) return 1;
__asm__ volatile("csrr %0, 0xB9C" : "=r"(reg));
__asm__ volatile("csrr %0, mhpmcounter28h" : "=r"(reg));
if(reg != 0) return 1;
__asm__ volatile("csrr %0, 0xB9D" : "=r"(reg));
__asm__ volatile("csrr %0, mhpmcounter29h" : "=r"(reg));
if(reg != 0) return 1;
__asm__ volatile("csrr %0, 0xB9E" : "=r"(reg));
__asm__ volatile("csrr %0, mhpmcounter30h" : "=r"(reg));
if(reg != 0) return 1;
__asm__ volatile("csrr %0, 0xB9F" : "=r"(reg));
__asm__ volatile("csrr %0, mhpmcounter31h" : "=r"(reg));
if(reg != 0) return 1;

return 0;
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