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Merge pull request openhwgroup#2296 from silabs-robin/xdev2sdev_merge…
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…_2023-11-20

Xdev2sdev merge 2023 11 20
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@silabs-robin
silabs-robin authored Dec 4, 2023
2 parents 4ae7e26 + eabbfa2 commit 25874b6
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Showing 10 changed files with 232 additions and 135 deletions.
3 changes: 1 addition & 2 deletions bin/clonetb
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Original file line number Diff line number Diff line change
Expand Up @@ -81,8 +81,7 @@ clone() {
clone_cv32e40x() {
CV_CORE=cv32e40x
VERIF_ENV_REPO=https://github.com/openhwgroup/cv32e40x-dv.git
VERIF_ENV_REF=443f11c

VERIF_ENV_REF=be17b8902002f91803abde4bfb8caa91088575e1
clone

ignore_cloned_directory
Expand Down
120 changes: 90 additions & 30 deletions bin/gen_csr_access_test.py
100644 → 100755
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Original file line number Diff line number Diff line change
@@ -1,10 +1,42 @@
#!/usr/bin/env python3


# Copyright 2023 Silicon Labs, Inc.
#
# SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
#
# Licensed under the Solderpad Hardware License v 2.1 (the "License"); you may
# not use this file except in compliance with the License, or, at your option,
# the Apache License version 2.0.
#
# You may obtain a copy of the License at
# https://solderpad.org/licenses/SHL-2.1/
#
# Unless required by applicable law or agreed to in writing, any work
# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
#
# See the License for the specific language governing permissions and
# limitations under the License.


# Description:
# This script is for generating the CSR access test:
# `cv32e40(s|x)/tests/programs/custom/cv32e40x_csr_access_test/`.
#
# It calls a generation script within `riscv-dv`.
# A Yaml config as per `--input_yaml_path` is used as its input.
# See the README in the path mention above for additional usage info.


import sys
import os
import argparse
import subprocess
import yaml
import shlex


if (sys.version_info < (3,5,0)):
print ('Requires python 3.5')
exit(1)
Expand Down Expand Up @@ -108,47 +140,28 @@ def run_riscv_dv_gen_csr_script(output_yaml_path):
print("error: exception in 'run_riscv_dv_gen_csr_script'")
print(e)

def preprocess_yaml():
input_script_path = yaml_file_path
w_enable = True
w_enable_n = w_enable
str_args = ""
enabled_features = {
"clic": False,
"clint": False,
"debug": False,
"e_base": False,
"i_base": False,
"m_ext": False,
"m_none": False,
"readonly": False,
"umode": False,
"a_ext": False,
"f_ext": False,
"p_ext": False,
"v_ext": False,
"x_ext": False,
"xsecure": False,
"zc": False,
"zicntr": False,
"marchid": 0,
"num_mhpmcounters": 0,
"pmp_num_regions": 0,
"dbg_num_triggers": 0,
}
def set_enabled_features(enabled_features_previous, str_args_previous, args):
enabled_features = enabled_features_previous
str_args = str_args_previous

# "VERIF_HEADER" (Design-workaround for CSR field alternatives.)
enabled_features["verif_header"] = True

# CLIC
if (args.clic_enable):
str_args = str_args + "_clic"
enabled_features["clic"] = True

# CLINT
if (args.clint_enable or not args.clic_enable):
str_args = str_args + "_clint"
enabled_features["clint"] = True if not enabled_features["clic"] else False

# DEBUG
if (args.debug_enable):
str_args = str_args + "_debug"
enabled_features["debug"] = True

# I/E
if (args.i_base_enable or args.i_ext_enable):
str_args = str_args + "_i"
Expand All @@ -161,6 +174,7 @@ def preprocess_yaml():
exit(1)
if (args.i_ext_enable or args.e_ext_enable):
print("warning: i and e are 'base' modules, not extensions", file=sys.stderr)

# M
if (args.m_ext_enable):
str_args = str_args + "_m"
Expand All @@ -171,59 +185,105 @@ def preprocess_yaml():
else:
print("error: need '--m_ext_enable' or '--m_none_enable'", file=sys.stderr)
exit(1)

# A_EXT
if (args.a_ext_enable):
str_args = str_args + "_a"
enabled_features["a_ext"] = True

# F_EXT
if (args.f_ext_enable):
str_args = str_args + "_f"
enabled_features["f_ext"] = True

# P_EXT
if (args.p_ext_enable):
str_args = str_args + "_p"
enabled_features["p_ext"] = True

# V_EXT
if (args.v_ext_enable):
str_args = str_args + "_v"
enabled_features["v_ext"] = True

# X_EXT
if (args.x_ext_enable):
str_args = str_args + "_x"
enabled_features["x_ext"] = True

# XSECURE
if (args.xsecure_enable):
str_args = str_args + "_xsecure"
enabled_features["xsecure"] = True

# UMODE
if (args.umode_enable):
str_args = str_args + "_umode"
enabled_features["umode"] = True

# ZC
if (args.zc_enable):
str_args = str_args + "_zc"
enabled_features["zc"] = True

# ZICNTR
if (args.zicntr_enable):
str_args = str_args + "_zicntr"
enabled_features["zicntr"] = True

# MARCHID
if (int(args.marchid) > 0):
str_args = str_args + "_marchid" + args.marchid
enabled_features["marchid"] = int(args.marchid)

# MHPMCOUNTERS
if (int(args.mhpmcounter_num) > 0):
str_args = str_args + "_mhpmctr" + args.mhpmcounter_num
enabled_features["num_mhpmcounters"] = int(args.mhpmcounter_num)

# PMP
if (int(args.pmp_num_regions) > 0):
str_args = str_args + "_pmp" + args.pmp_num_regions
enabled_features["pmp_num_regions"] = int(args.pmp_num_regions)

# TRIGGERS
if (int(args.num_triggers) > 0):
str_args = str_args + "_triggers" + args.num_triggers
enabled_features["dbg_num_triggers"] = int(args.num_triggers)
# TODO:silabs-robin Any other "enabled_features"?

return (enabled_features, str_args)

def preprocess_yaml():
input_script_path = yaml_file_path
w_enable = True
w_enable_n = w_enable
str_args = ""
enabled_features = {
"clic": False,
"clint": False,
"debug": False,
"e_base": False,
"i_base": False,
"m_ext": False,
"m_none": False,
"readonly": False,
"umode": False,
"a_ext": False,
"f_ext": False,
"p_ext": False,
"v_ext": False,
"x_ext": False,
"xsecure": False,
"zc": False,
"zicntr": False,
"marchid": 0,
"num_mhpmcounters": 0,
"pmp_num_regions": 0,
"dbg_num_triggers": 0,
}

(enabled_features, str_args) = \
set_enabled_features(enabled_features, str_args, args)

print("enabled_features: {}".format(enabled_features))

Expand Down Expand Up @@ -320,7 +380,7 @@ def preprocess_yaml_m4(enabled_features, input_script_path, output_script_handle

# Run the preprocessing
args = args_pre + args_mid + args_post
print('running m4 as: ' + str(args)) # TODO:silabs-robin "if '--verbose'"
print('running m4 as: ' + str(args))
proc_results = subprocess.run(args, stdout=output_script_handle)

if proc_results.returncode != 0:
Expand Down
20 changes: 10 additions & 10 deletions ...40s/tb/uvmt/uvmt_cv32e40s_umode_assert.sv → .../assertions/uvmt_cv32e40s_umode_assert.sv
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Original file line number Diff line number Diff line change
Expand Up @@ -932,21 +932,21 @@ module uvmt_cv32e40s_umode_assert

// vplan:InstrProt

a_instr_prot: assert property (
a_rvfi_instr_prot: assert property (
rvfi_valid
|->
(rvfi_if.instr_prot[2:1] == rvfi_if.rvfi_mode) ||
(rvfi_if.rvfi_instr_prot[2:1] == rvfi_if.rvfi_mode) ||
(rvfi_if.rvfi_trap.exception_cause == cv32e40s_pkg::EXC_CAUSE_INSTR_FAULT) ||
(rvfi_trap.debug_cause == DBG_CAUSE_TRIGGER)
//Note: Triggers can overshadow access faults
) else `uvm_error(info_tag, "the prot on fetch must match the mode on retirement");

a_instr_prot_legal: assert property (
a_rvfi_instr_prot_legal: assert property (
rvfi_valid &&
(rvfi_if.rvfi_trap.exception_cause != cv32e40s_pkg::EXC_CAUSE_INSTR_FAULT)
|->
(rvfi_if.instr_prot[2:0] inside {3'b 000, 3'b 110})
) else `uvm_error(info_tag, "instr_prot illegal value");
(rvfi_if.rvfi_instr_prot[2:0] inside {3'b 000, 3'b 110})
) else `uvm_error(info_tag, "rvfi_instr_prot illegal value");

a_prot_iside_legal: assert property (
obi_iside_prot inside {3'b 000, 3'b 110}
Expand All @@ -959,14 +959,14 @@ module uvmt_cv32e40s_umode_assert
rvfi_valid &&
(rvfi_if.rvfi_mem_rmask || rvfi_if.rvfi_mem_wmask)
|->
(rvfi_if.mem_prot[2:1] == effective_rvfi_privmode)
(rvfi_if.rvfi_mem_prot[2:1] == effective_rvfi_privmode)
) else `uvm_error(info_tag, "the prot on load/store must match the effective mode on retirement");

a_data_prot_legal: assert property (
rvfi_valid &&
(rvfi_if.rvfi_trap.exception_cause != cv32e40s_pkg::EXC_CAUSE_INSTR_FAULT)
|->
(rvfi_if.mem_prot[2:0] inside {3'b 001, 3'b 111})
(rvfi_if.rvfi_mem_prot[2:0] inside {3'b 001, 3'b 111})
) else `uvm_error(info_tag, "data_prot illegal value");

a_prot_dside_legal: assert property (
Expand All @@ -977,7 +977,7 @@ module uvmt_cv32e40s_umode_assert
logic [NMEM-1:0] mem_act;
for (genvar i = 0; i < NMEM; i++) begin: gen_data_prot_equals
always_comb begin
data_prot_equals[i] = (rvfi_if.mem_prot[i*3+:3] == rvfi_if.mem_prot[2:0]);
data_prot_equals[i] = (rvfi_if.rvfi_mem_prot[i*3+:3] == rvfi_if.rvfi_mem_prot[2:0]);
mem_act[i] = |rvfi_if.check_mem_act(i);
end
end
Expand Down Expand Up @@ -1008,7 +1008,7 @@ module uvmt_cv32e40s_umode_assert
rvfi_if.rvfi_valid &&
rvfi_if.rvfi_dbg_mode
|->
(rvfi_if.instr_prot[2:1] == MODE_M) ||
(rvfi_if.rvfi_instr_prot[2:1] == MODE_M) ||
(rvfi_if.rvfi_trap.exception_cause == cv32e40s_pkg::EXC_CAUSE_INSTR_FAULT)
) else `uvm_error(info_tag, "dmode should fetch as mmode");

Expand All @@ -1017,7 +1017,7 @@ module uvmt_cv32e40s_umode_assert
rvfi_valid &&
(|rvfi_if.rvfi_mem_rmask || |rvfi_if.rvfi_mem_wmask)
|->
(rvfi_if.mem_prot[2:1] == effective_rvfi_privmode)
(rvfi_if.rvfi_mem_prot[2:1] == effective_rvfi_privmode)
) else `uvm_error(info_tag, "dmode should fetch as effective mode");


Expand Down
0 cv32e40s/tb/uvmt/uvmt_cv32e40s_umode_cov.sv → .../tb/assertions/uvmt_cv32e40s_umode_cov.sv
View file
File renamed without changes.
88 changes: 49 additions & 39 deletions cv32e40s/tb/uvmt/uvmt_cv32e40s_tb.sv
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Original file line number Diff line number Diff line change
Expand Up @@ -164,45 +164,55 @@ module uvmt_cv32e40s_tb;
// "rvfi_instr_if"

bind cv32e40s_wrapper
uvma_rvfi_instr_if_t#(uvmt_cv32e40s_base_test_pkg::ILEN,
uvmt_cv32e40s_base_test_pkg::XLEN) rvfi_instr_if(.clk(clk_i),
.reset_n(rst_ni),

.rvfi_valid(rvfi_i.rvfi_valid[0]),
.rvfi_order(rvfi_i.rvfi_order[uvma_rvfi_pkg::ORDER_WL*0+:uvma_rvfi_pkg::ORDER_WL]),
.rvfi_insn(rvfi_i.rvfi_insn[uvmt_cv32e40s_base_test_pkg::ILEN*0+:uvmt_cv32e40s_base_test_pkg::ILEN]),
.rvfi_trap(rvfi_i.rvfi_trap),
.rvfi_halt(rvfi_i.rvfi_halt[0]),
.rvfi_intr(rvfi_i.rvfi_intr),
.rvfi_dbg(rvfi_i.rvfi_dbg),
.rvfi_dbg_mode(rvfi_i.rvfi_dbg_mode),
.rvfi_nmip(rvfi_i.rvfi_nmip),
.rvfi_mode(rvfi_i.rvfi_mode[uvma_rvfi_pkg::MODE_WL*0+:uvma_rvfi_pkg::MODE_WL]),
.rvfi_ixl(rvfi_i.rvfi_ixl[uvma_rvfi_pkg::IXL_WL*0+:uvma_rvfi_pkg::IXL_WL]),
.rvfi_pc_rdata(rvfi_i.rvfi_pc_rdata[uvmt_cv32e40s_base_test_pkg::XLEN*0+:uvmt_cv32e40s_base_test_pkg::XLEN]),
.rvfi_pc_wdata(rvfi_i.rvfi_pc_wdata[uvmt_cv32e40s_base_test_pkg::XLEN*0+:uvmt_cv32e40s_base_test_pkg::XLEN]),
.rvfi_rs1_addr(rvfi_i.rvfi_rs1_addr[uvma_rvfi_pkg::GPR_ADDR_WL*0+:uvma_rvfi_pkg::GPR_ADDR_WL]),
.rvfi_rs1_rdata(rvfi_i.rvfi_rs1_rdata[uvmt_cv32e40s_base_test_pkg::XLEN*0+:uvmt_cv32e40s_base_test_pkg::XLEN]),
.rvfi_rs2_addr(rvfi_i.rvfi_rs2_addr[uvma_rvfi_pkg::GPR_ADDR_WL*0+:uvma_rvfi_pkg::GPR_ADDR_WL]),
.rvfi_rs2_rdata(rvfi_i.rvfi_rs2_rdata[uvmt_cv32e40s_base_test_pkg::XLEN*0+:uvmt_cv32e40s_base_test_pkg::XLEN]),
.rvfi_rs3_addr('0),
.rvfi_rs3_rdata('0),
.rvfi_rd1_addr(rvfi_i.rvfi_rd_addr[uvma_rvfi_pkg::GPR_ADDR_WL*0+:uvma_rvfi_pkg::GPR_ADDR_WL]),
.rvfi_rd1_wdata(rvfi_i.rvfi_rd_wdata[uvmt_cv32e40s_base_test_pkg::XLEN*0+:uvmt_cv32e40s_base_test_pkg::XLEN]),
.rvfi_rd2_addr('0),
.rvfi_rd2_wdata('0),
.rvfi_gpr_rdata(rvfi_i.rvfi_gpr_rdata[32*uvmt_cv32e40s_base_test_pkg::XLEN*0 +:32*uvmt_cv32e40s_base_test_pkg::XLEN]),
.rvfi_gpr_rmask(rvfi_i.rvfi_gpr_rmask[32*0 +:32]),
.rvfi_gpr_wdata(rvfi_i.rvfi_gpr_wdata[32*uvmt_cv32e40s_base_test_pkg::XLEN*0 +:32*uvmt_cv32e40s_base_test_pkg::XLEN]),
.rvfi_gpr_wmask(rvfi_i.rvfi_gpr_wmask[32*0 +:32]),
.rvfi_mem_addr(rvfi_i.rvfi_mem_addr[ uvma_rvfi_pkg::NMEM*uvmt_cv32e40s_base_test_pkg::XLEN*0 +:uvma_rvfi_pkg::NMEM*uvmt_cv32e40s_base_test_pkg::XLEN]),
.rvfi_mem_rdata(rvfi_i.rvfi_mem_rdata[uvma_rvfi_pkg::NMEM*uvmt_cv32e40s_base_test_pkg::XLEN*0 +:uvma_rvfi_pkg::NMEM*uvmt_cv32e40s_base_test_pkg::XLEN]),
.rvfi_mem_rmask(rvfi_i.rvfi_mem_rmask[uvma_rvfi_pkg::NMEM*uvmt_cv32e40s_base_test_pkg::XLEN/8*0 +:uvma_rvfi_pkg::NMEM*uvmt_cv32e40s_base_test_pkg::XLEN/8]),
.rvfi_mem_wdata(rvfi_i.rvfi_mem_wdata[uvma_rvfi_pkg::NMEM*uvmt_cv32e40s_base_test_pkg::XLEN*0 +:uvma_rvfi_pkg::NMEM*uvmt_cv32e40s_base_test_pkg::XLEN]),
.rvfi_mem_wmask(rvfi_i.rvfi_mem_wmask[uvma_rvfi_pkg::NMEM*uvmt_cv32e40s_base_test_pkg::XLEN/8*0 +:uvma_rvfi_pkg::NMEM*uvmt_cv32e40s_base_test_pkg::XLEN/8]),
.instr_prot(rvfi_i.rvfi_instr_prot),
.mem_prot(rvfi_i.rvfi_mem_prot)
);
uvma_rvfi_instr_if_t#(
uvmt_cv32e40s_base_test_pkg::ILEN,
uvmt_cv32e40s_base_test_pkg::XLEN
) rvfi_instr_if(
.clk (clk_i),
.reset_n (rst_ni),

.rvfi_valid (rvfi_i.rvfi_valid[0]),
.rvfi_order (rvfi_i.rvfi_order[uvma_rvfi_pkg::ORDER_WL*0+:uvma_rvfi_pkg::ORDER_WL]),
.rvfi_insn (rvfi_i.rvfi_insn[uvmt_cv32e40s_base_test_pkg::ILEN*0+:uvmt_cv32e40s_base_test_pkg::ILEN]),
.rvfi_trap (rvfi_i.rvfi_trap),
.rvfi_halt (rvfi_i.rvfi_halt[0]),
.rvfi_intr (rvfi_i.rvfi_intr),
.rvfi_dbg (rvfi_i.rvfi_dbg),
.rvfi_dbg_mode (rvfi_i.rvfi_dbg_mode),
.rvfi_nmip (rvfi_i.rvfi_nmip),
.rvfi_mode (rvfi_i.rvfi_mode[uvma_rvfi_pkg::MODE_WL*0+:uvma_rvfi_pkg::MODE_WL]),
.rvfi_ixl (rvfi_i.rvfi_ixl[uvma_rvfi_pkg::IXL_WL*0+:uvma_rvfi_pkg::IXL_WL]),
.rvfi_pc_rdata (rvfi_i.rvfi_pc_rdata[uvmt_cv32e40s_base_test_pkg::XLEN*0+:uvmt_cv32e40s_base_test_pkg::XLEN]),
.rvfi_pc_wdata (rvfi_i.rvfi_pc_wdata[uvmt_cv32e40s_base_test_pkg::XLEN*0+:uvmt_cv32e40s_base_test_pkg::XLEN]),
.rvfi_rs1_addr (rvfi_i.rvfi_rs1_addr[uvma_rvfi_pkg::GPR_ADDR_WL*0+:uvma_rvfi_pkg::GPR_ADDR_WL]),
.rvfi_rs1_rdata (rvfi_i.rvfi_rs1_rdata[uvmt_cv32e40s_base_test_pkg::XLEN*0+:uvmt_cv32e40s_base_test_pkg::XLEN]),
.rvfi_rs2_addr (rvfi_i.rvfi_rs2_addr[uvma_rvfi_pkg::GPR_ADDR_WL*0+:uvma_rvfi_pkg::GPR_ADDR_WL]),
.rvfi_rs2_rdata (rvfi_i.rvfi_rs2_rdata[uvmt_cv32e40s_base_test_pkg::XLEN*0+:uvmt_cv32e40s_base_test_pkg::XLEN]),
.rvfi_rs3_addr ('0),
.rvfi_rs3_rdata ('0),
.rvfi_rd1_addr (rvfi_i.rvfi_rd_addr[uvma_rvfi_pkg::GPR_ADDR_WL*0+:uvma_rvfi_pkg::GPR_ADDR_WL]),
.rvfi_rd1_wdata (rvfi_i.rvfi_rd_wdata[uvmt_cv32e40s_base_test_pkg::XLEN*0+:uvmt_cv32e40s_base_test_pkg::XLEN]),
.rvfi_rd2_addr ('0),
.rvfi_rd2_wdata ('0),
.rvfi_gpr_rdata (rvfi_i.rvfi_gpr_rdata[32*uvmt_cv32e40s_base_test_pkg::XLEN*0 +:32*uvmt_cv32e40s_base_test_pkg::XLEN]),
.rvfi_gpr_rmask (rvfi_i.rvfi_gpr_rmask[32*0 +:32]),
.rvfi_gpr_wdata (rvfi_i.rvfi_gpr_wdata[32*uvmt_cv32e40s_base_test_pkg::XLEN*0 +:32*uvmt_cv32e40s_base_test_pkg::XLEN]),
.rvfi_gpr_wmask (rvfi_i.rvfi_gpr_wmask[32*0 +:32]),
.rvfi_mem_addr (rvfi_i.rvfi_mem_addr[ uvma_rvfi_pkg::NMEM*uvmt_cv32e40s_base_test_pkg::XLEN*0 +:uvma_rvfi_pkg::NMEM*uvmt_cv32e40s_base_test_pkg::XLEN]),
.rvfi_mem_rdata (rvfi_i.rvfi_mem_rdata[uvma_rvfi_pkg::NMEM*uvmt_cv32e40s_base_test_pkg::XLEN*0 +:uvma_rvfi_pkg::NMEM*uvmt_cv32e40s_base_test_pkg::XLEN]),
.rvfi_mem_rmask (rvfi_i.rvfi_mem_rmask[uvma_rvfi_pkg::NMEM*uvmt_cv32e40s_base_test_pkg::XLEN/8*0 +:uvma_rvfi_pkg::NMEM*uvmt_cv32e40s_base_test_pkg::XLEN/8]),
.rvfi_mem_wdata (rvfi_i.rvfi_mem_wdata[uvma_rvfi_pkg::NMEM*uvmt_cv32e40s_base_test_pkg::XLEN*0 +:uvma_rvfi_pkg::NMEM*uvmt_cv32e40s_base_test_pkg::XLEN]),
.rvfi_mem_wmask (rvfi_i.rvfi_mem_wmask[uvma_rvfi_pkg::NMEM*uvmt_cv32e40s_base_test_pkg::XLEN/8*0 +:uvma_rvfi_pkg::NMEM*uvmt_cv32e40s_base_test_pkg::XLEN/8]),
.rvfi_instr_prot (rvfi_i.rvfi_instr_prot),
.rvfi_instr_memtype (rvfi_i.rvfi_instr_memtype),
.rvfi_instr_dbg (rvfi_i.rvfi_instr_dbg),
.rvfi_mem_prot (rvfi_i.rvfi_mem_prot),
.rvfi_mem_exokay (rvfi_i.rvfi_mem_exokay),
.rvfi_mem_err (rvfi_i.rvfi_mem_err),
.rvfi_mem_atop (rvfi_i.rvfi_mem_atop),
.rvfi_mem_memtype (rvfi_i.rvfi_mem_memtype),
.rvfi_mem_dbg (rvfi_i.rvfi_mem_dbg)
);

// RVFI CSR binds
`RVFI_CSR_BIND(cpuctrl)
Expand Down
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