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Sifive rvv intrinsic xsfvcp #7

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Sifive rvv intrinsic xsfvcp #7

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35e6c55
RISC-V: Update Xsfvfnrclip implementation.
pz9115 Dec 13, 2024
5c5a2cb
RISC-V: Update Xsfvqmacc and Xsfvfnrclip's testcases
Liaoshihua Dec 10, 2024
8e239d8
RISC-V: Add intrinsics support for SiFive Xsfvcp extensions.
yulong18 Dec 19, 2024
bcc379f
RISC-V: Add intrinsic testcases for SiFive Xsfvcp extensions.
Liaoshihua Dec 18, 2024
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10 changes: 10 additions & 0 deletions gcc/config/riscv/constraints.md
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Original file line number Diff line number Diff line change
Expand Up @@ -295,3 +295,13 @@
"Shifting immediate for SIMD shufflei3."
(and (match_code "const_int")
(match_test "IN_RANGE (ival, -64, -1)")))

(define_constraint "Ou01"
"A 1-bit unsigned immediate."
(and (match_code "const_int")
(match_test "IN_RANGE (ival, 0, 1)")))

(define_constraint "Ou02"
"A 2-bit unsigned immediate."
(and (match_code "const_int")
(match_test "IN_RANGE (ival, 0, 3)")))
4 changes: 4 additions & 0 deletions gcc/config/riscv/generic-vector-ooo.md
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Expand Up @@ -141,3 +141,7 @@
(eq_attr "type" "rdvlenb,rdvl")
"vxu_ooo_issue,vxu_ooo_issue")

;; Vector sf_vcp.
(define_insn_reservation "vec_sf_vcp" 2
(eq_attr "type" "sf_vc,sf_vc_se")
"vxu_ooo_issue")
26 changes: 26 additions & 0 deletions gcc/config/riscv/genrvv-type-indexer.cc
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Expand Up @@ -164,6 +164,18 @@ floattype (unsigned sew, int lmul_log2)
return mode.str ();
}

std::string
expand_floattype (unsigned sew, int lmul_log2, unsigned nf)
{
if (sew != 8 || nf!= 1
|| (!valid_type (sew * 4, lmul_log2 + 2, /*float_t*/ true)))
return "INVALID";

std::stringstream mode;
mode << "vfloat" << sew * 4 << to_lmul (lmul_log2 + 2) << "_t";
return mode.str ();
}

std::string
floattype (unsigned sew, int lmul_log2, unsigned nf)
{
Expand Down Expand Up @@ -276,6 +288,7 @@ main (int argc, const char **argv)
fprintf (fp, " /*QLMUL1*/ INVALID,\n");
fprintf (fp, " /*QLMUL1_SIGNED*/ INVALID,\n");
fprintf (fp, " /*QLMUL1_UNSIGNED*/ INVALID,\n");
fprintf (fp, " /*XFQF*/ INVALID,\n");
for (unsigned eew : {8, 16, 32, 64})
fprintf (fp, " /*EEW%d_INTERPRET*/ INVALID,\n", eew);

Expand All @@ -290,6 +303,8 @@ main (int argc, const char **argv)
fprintf (fp, " /*UNSIGNED_EEW%d_LMUL1_INTERPRET*/ %s,\n", eew,
inttype (eew, LMUL1_LOG2, /* unsigned_p */true).c_str ());

fprintf (fp, " /*X2*/ INVALID,\n");

for (unsigned lmul_log2_offset : {1, 2, 3, 4, 5, 6})
{
unsigned multiple_of_lmul = 1 << lmul_log2_offset;
Expand Down Expand Up @@ -384,6 +399,8 @@ main (int argc, const char **argv)
inttype (8, /*lmul_log2*/ 0, false).c_str ());
fprintf (fp, " /*QLMUL1_UNSIGNED*/ %s,\n",
inttype (8, /*lmul_log2*/ 0, true).c_str ());
fprintf (fp, " /*XFQF*/ %s,\n",
expand_floattype (sew, lmul_log2, nf).c_str ());
for (unsigned eew : {8, 16, 32, 64})
{
if (eew == sew)
Expand Down Expand Up @@ -411,6 +428,9 @@ main (int argc, const char **argv)
fprintf (fp, " /*UNSIGNED_EEW%d_LMUL1_INTERPRET*/ INVALID,\n",
eew);

fprintf (fp, " /*X2*/ %s,\n",
inttype (sew * 2, lmul_log2 + 1, /*unsigned_p*/ true).c_str ());

for (unsigned lmul_log2_offset : {1, 2, 3, 4, 5, 6})
{
unsigned multiple_of_lmul = 1 << lmul_log2_offset;
Expand Down Expand Up @@ -473,6 +493,7 @@ main (int argc, const char **argv)
bfloat16_wide_type (/*lmul_log2*/ 0).c_str ());
fprintf (fp, " /*QLMUL1_SIGNED*/ INVALID,\n");
fprintf (fp, " /*QLMUL1_UNSIGNED*/ INVALID,\n");
fprintf (fp, " /*XFQF*/ INVALID,\n");
for (unsigned eew : {8, 16, 32, 64})
fprintf (fp, " /*EEW%d_INTERPRET*/ INVALID,\n", eew);

Expand All @@ -485,6 +506,8 @@ main (int argc, const char **argv)
for (unsigned eew : EEW_SIZE_LIST)
fprintf (fp, " /*UNSIGNED_EEW%d_LMUL1_INTERPRET*/ INVALID,\n", eew);

fprintf (fp, " /*X2*/ INVALID,\n");

for (unsigned lmul_log2_offset : {1, 2, 3, 4, 5, 6})
{
unsigned multiple_of_lmul = 1 << lmul_log2_offset;
Expand Down Expand Up @@ -558,6 +581,7 @@ main (int argc, const char **argv)
floattype (sew / 4, /*lmul_log2*/ 0).c_str ());
fprintf (fp, " /*QLMUL1_SIGNED*/ INVALID,\n");
fprintf (fp, " /*QLMUL1_UNSIGNED*/ INVALID,\n");
fprintf (fp, " /*XFQF*/ INVALID,\n");
for (unsigned eew : {8, 16, 32, 64})
fprintf (fp, " /*EEW%d_INTERPRET*/ INVALID,\n", eew);

Expand All @@ -571,6 +595,8 @@ main (int argc, const char **argv)
fprintf (fp, " /*UNSIGNED_EEW%d_LMUL1_INTERPRET*/ INVALID,\n",
eew);

fprintf (fp, " /*X2*/ INVALID,\n");

for (unsigned lmul_log2_offset : {1, 2, 3, 4, 5, 6})
{
unsigned multiple_of_lmul = 1 << lmul_log2_offset;
Expand Down
48 changes: 48 additions & 0 deletions gcc/config/riscv/riscv-vector-builtins-shapes.cc
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Expand Up @@ -1343,6 +1343,52 @@ struct sf_vfnrclip_def : public build_base
}
};

/* sf_vcix_se_def class. */
struct sf_vcix_se_def : public build_base
{
char *get_name (function_builder &b, const function_instance &instance,
bool overloaded_p) const override
{
/* Return nullptr if it is overloaded. */
if (overloaded_p)
return nullptr;

b.append_base_name (instance.base_name);

/* vop --> vop<op>_se_<type>. */
if (!overloaded_p)
{
b.append_name (operand_suffixes[instance.op_info->op]);
b.append_name ("_se");
b.append_name (type_suffixes[instance.type.index].vector);
}
return b.finish_name ();
}
};

/* sf_vcix_def class. */
struct sf_vcix_def : public build_base
{
char *get_name (function_builder &b, const function_instance &instance,
bool overloaded_p) const override
{
/* Return nullptr if it is overloaded. */
if (overloaded_p)
return nullptr;

b.append_base_name (instance.base_name);

/* vop --> vop_<type>. */
if (!overloaded_p)
{
b.append_name (operand_suffixes[instance.op_info->op]);
b.append_name (type_suffixes[instance.type.index].vector);
}
return b.finish_name ();
}
};


SHAPE(vsetvl, vsetvl)
SHAPE(vsetvl, vsetvlmax)
SHAPE(loadstore, loadstore)
Expand Down Expand Up @@ -1379,4 +1425,6 @@ SHAPE(crypto_vi, crypto_vi)
SHAPE(crypto_vv_no_op_type, crypto_vv_no_op_type)
SHAPE (sf_vqmacc, sf_vqmacc)
SHAPE (sf_vfnrclip, sf_vfnrclip)
SHAPE(sf_vcix_se, sf_vcix_se)
SHAPE(sf_vcix, sf_vcix)
} // end namespace riscv_vector
2 changes: 2 additions & 0 deletions gcc/config/riscv/riscv-vector-builtins-shapes.h
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Original file line number Diff line number Diff line change
Expand Up @@ -62,6 +62,8 @@ extern const function_shape *const crypto_vv_no_op_type;
/* Sifive vendor extension. */
extern const function_shape *const sf_vqmacc;
extern const function_shape *const sf_vfnrclip;
extern const function_shape *const sf_vcix_se;
extern const function_shape *const sf_vcix;
}

} // end namespace riscv_vector
Expand Down
53 changes: 53 additions & 0 deletions gcc/config/riscv/riscv-vector-builtins-types.def
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Expand Up @@ -363,6 +363,24 @@ along with GCC; see the file COPYING3. If not see
#define DEF_RVV_QMACC_OPS(TYPE, REQUIRE)
#endif

/* Use "DEF_RVV_XFQF_OPS" macro include signed integer which will
be iterated and registered as intrinsic functions. */
#ifndef DEF_RVV_XFQF_OPS
#define DEF_RVV_XFQF_OPS(TYPE, REQUIRE)
#endif

/* Use "DEF_RVV_X2_U_OPS" macro include unsigned integer which will
be iterated and registered as intrinsic functions. */
#ifndef DEF_RVV_X2_U_OPS
#define DEF_RVV_X2_U_OPS(TYPE, REQUIRE)
#endif

/* Use "DEF_RVV_X2_WU_OPS" macro include widen unsigned integer which will
be iterated and registered as intrinsic functions. */
#ifndef DEF_RVV_X2_WU_OPS
#define DEF_RVV_X2_WU_OPS(TYPE, REQUIRE)
#endif

DEF_RVV_I_OPS (vint8mf8_t, RVV_REQUIRE_MIN_VLEN_64)
DEF_RVV_I_OPS (vint8mf4_t, 0)
DEF_RVV_I_OPS (vint8mf2_t, 0)
Expand Down Expand Up @@ -1451,6 +1469,38 @@ DEF_RVV_QMACC_OPS (vint32m2_t, 0)
DEF_RVV_QMACC_OPS (vint32m4_t, 0)
DEF_RVV_QMACC_OPS (vint32m8_t, 0)

DEF_RVV_XFQF_OPS (vint8mf8_t, 0)
DEF_RVV_XFQF_OPS (vint8mf4_t, 0)
DEF_RVV_XFQF_OPS (vint8mf2_t, 0)
DEF_RVV_XFQF_OPS (vint8m1_t, 0)
DEF_RVV_XFQF_OPS (vint8m2_t, 0)

DEF_RVV_X2_U_OPS (vuint8mf8_t, RVV_REQUIRE_MIN_VLEN_64)
DEF_RVV_X2_U_OPS (vuint8mf4_t, 0)
DEF_RVV_X2_U_OPS (vuint8mf2_t, 0)
DEF_RVV_X2_U_OPS (vuint8m1_t, 0)
DEF_RVV_X2_U_OPS (vuint8m2_t, 0)
DEF_RVV_X2_U_OPS (vuint8m4_t, 0)
DEF_RVV_X2_U_OPS (vuint16mf4_t, RVV_REQUIRE_MIN_VLEN_64)
DEF_RVV_X2_U_OPS (vuint16mf2_t, 0)
DEF_RVV_X2_U_OPS (vuint16m1_t, 0)
DEF_RVV_X2_U_OPS (vuint16m2_t, 0)
DEF_RVV_X2_U_OPS (vuint16m4_t, 0)
DEF_RVV_X2_U_OPS (vuint32mf2_t, RVV_REQUIRE_MIN_VLEN_64)
DEF_RVV_X2_U_OPS (vuint32m1_t, 0)
DEF_RVV_X2_U_OPS (vuint32m2_t, 0)
DEF_RVV_X2_U_OPS (vuint32m4_t, 0)

DEF_RVV_X2_WU_OPS (vuint16mf4_t, RVV_REQUIRE_MIN_VLEN_64)
DEF_RVV_X2_WU_OPS (vuint16mf2_t, 0)
DEF_RVV_X2_WU_OPS (vuint16m1_t, 0)
DEF_RVV_X2_WU_OPS (vuint16m2_t, 0)
DEF_RVV_X2_WU_OPS (vuint16m4_t, 0)
DEF_RVV_X2_WU_OPS (vuint32mf2_t, RVV_REQUIRE_MIN_VLEN_64)
DEF_RVV_X2_WU_OPS (vuint32m1_t, 0)
DEF_RVV_X2_WU_OPS (vuint32m2_t, 0)
DEF_RVV_X2_WU_OPS (vuint32m4_t, 0)

#undef DEF_RVV_I_OPS
#undef DEF_RVV_U_OPS
#undef DEF_RVV_F_OPS
Expand Down Expand Up @@ -1506,3 +1556,6 @@ DEF_RVV_QMACC_OPS (vint32m8_t, 0)
#undef DEF_RVV_CRYPTO_SEW64_OPS
#undef DEF_RVV_F32_OPS
#undef DEF_RVV_QMACC_OPS
#undef DEF_RVV_XFQF_OPS
#undef DEF_RVV_X2_U_OPS
#undef DEF_RVV_X2_WU_OPS
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