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Add BSP for SparkFun RED-V board #620

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Add BSP for SparkFun RED-V board #620

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e389d5e
Initial attempt at sparkfun-redv BSP
danak6jq Feb 3, 2021
6fc2855
Update README.md for Sparkfun RED-V
danak6jq Feb 3, 2021
f2d589a
Merge branch 'sifive:master' into master
danak6jq Aug 31, 2021
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13 changes: 13 additions & 0 deletions bsp/sparkfun-redv/README.md
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Sparkfun RED-V is a low-cost, Arduino-compatible development board featuring the Freedom E310. It’s one of the best ways to start prototyping and developing your RISC‑V applications.

This target is ideal for getting familiar with the RISC-V ISA instruction set and the freedom-metal libraries. It supports:

- 1 hart with RV32IMAC core
- 4 hardware breakpoints
- Physical Memory Protection with 8 regions
- 16 local interrupts signal that can be connected to off core complex devices
- Up to 127 PLIC interrupt signals that can be connected to off core complex devices, with 7 priority levels
- GPIO memory with 16 interrupt lines
- SPI memory with 1 interrupt line
- Serial port with 1 interrupt line
- 1 blue LED
250 changes: 250 additions & 0 deletions bsp/sparkfun-redv/core.dts
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/dts-v1/;
/ {
#address-cells = <1>;
#size-cells = <1>;
compatible = "sparkfun,redv";
model = "sparkfun,rev";
cpus {
#address-cells = <1>;
#size-cells = <0>;
compatible = "sifive,fe310-g000";
L6: cpu@0 {
clocks = <&hfclk>;
compatible = "sifive,rocket0", "riscv";
device_type = "cpu";
i-cache-block-size = <64>;
i-cache-sets = <128>;
i-cache-size = <16384>;
next-level-cache = <&spi0>;
reg = <0>;
riscv,isa = "rv32imac";
riscv,pmpregions = <8>;
sifive,itim = <&itim>;
sifive,dtim = <&dtim>;
status = "okay";
timebase-frequency = <16000000>;
hardware-exec-breakpoint-count = <4>;
hlic: interrupt-controller {
#interrupt-cells = <1>;
compatible = "riscv,cpu-intc";
interrupt-controller;
};
};
};
soc {
#address-cells = <1>;
#size-cells = <1>;
#clock-cells = <1>;
compatible = "sifive,hifive1";
ranges;
hfxoscin: clock@0 {
#clock-cells = <0>;
compatible = "fixed-clock";
clock-frequency = <16000000>;
};
hfxoscout: clock@1 {
compatible = "sifive,fe310-g000,hfxosc";
clocks = <&hfxoscin>;
reg = <&prci 0x4>;
reg-names = "config";
};
hfroscin: clock@2 {
#clock-cells = <0>;
compatible = "fixed-clock";
clock-frequency = <72000000>;
};
hfroscout: clock@3 {
compatible = "sifive,fe310-g000,hfrosc";
clocks = <&hfroscin>;
reg = <&prci 0x0>;
reg-names = "config";
};
hfclk: clock@4 {
compatible = "sifive,fe310-g000,pll";
clocks = <&hfxoscout &hfroscout>;
clock-names = "pllref", "pllsel0";
reg = <&prci 0x8 &prci 0xc>;
reg-names = "config", "divider";
clock-frequency = <16000000>;
};
lfrosc: clock@5 {
#clock-cells = <0>;
compatible = "fixed-clock";
clock-frequency = <32768>;
};
psdlfaltclk: clock@6 {
#clock-cells = <0>;
compatible = "fixed-clock";
clock-frequency = <32768>;
};
lfclk: clock@7 {
compatible = "sifive,fe310-g000,lfrosc";
clocks = <&lfrosc &psdlfaltclk>;
clock-names = "lfrosc", "psdlfaltclk";
reg = <&aon 0x70 &aon 0x7C>;
reg-names = "config", "mux";
};
debug-controller@0 {
compatible = "sifive,debug-011", "riscv,debug-011";
interrupts-extended = <&hlic 65535>;
reg = <0x0 0x1000>;
reg-names = "control";
};
/* Missing: Error device */
maskrom@1000 {
reg = <0x1000 0x2000>;
reg-names = "mem";
};
otp@20000 {
reg = <0x20000 0x2000 0x10010000 0x1000>;
reg-names = "mem", "control";
};
clint: clint@2000000 {
compatible = "riscv,clint0";
interrupts-extended = <&hlic 3 &hlic 7>;
reg = <0x2000000 0x10000>;
reg-names = "control";
};
itim: itim@8000000 {
compatible = "sifive,itim0";
reg = <0x8000000 0x2000>;
reg-names = "mem";
};
plic: interrupt-controller@c000000 {
#interrupt-cells = <1>;
compatible = "riscv,plic0";
interrupt-controller;
interrupts-extended = <&hlic 11>;
reg = <0xc000000 0x4000000>;
reg-names = "control";
riscv,max-priority = <7>;
riscv,ndev = <52>;
};
aon: aon@10000000 {
compatible = "sifive,aon0";
reg = <0x10000000 0x8000>;
reg-names = "mem";
interrupt-parent = <&plic>;
interrupts = <1 2>;
clocks = <&lfclk>;
};
prci: prci@10008000 {
compatible = "sifive,fe310-g000,prci";
reg = <0x10008000 0x8000>;
reg-names = "mem";
};
gpio0: gpio@10012000 {
compatible = "sifive,gpio0";
interrupt-parent = <&plic>;
interrupts = <8 9 10 11 12 13 14 15 16 17 18 19 20 21 22
23 24 25 26 27 28 29 30 31 32 33 34 35 36
27 28 29>;
reg = <0x10012000 0x1000>;
reg-names = "control";
};
led@0 {
compatible = "sifive,gpio-leds";
label = "LD0";
gpios = <&gpio0 5>;
linux,default-trigger = "none";
};
uart0: serial@10013000 {
compatible = "sifive,uart0";
interrupt-parent = <&plic>;
interrupts = <3>;
reg = <0x10013000 0x1000>;
reg-names = "control";
clocks = <&hfclk>;
pinmux = <&gpio0 0x0 0x30000>;
};
spi0: spi@10014000 {
compatible = "sifive,spi0";
interrupt-parent = <&plic>;
interrupts = <5>;
reg = <0x10014000 0x1000 0x20000000 0x7A120>;
reg-names = "control", "mem";
clocks = <&hfclk>;
pinmux = <&gpio0 0x0 0x0>;
#address-cells = <1>;
#size-cells = <1>;
flash@0 {
compatible = "jedec,spi-nor";
reg = <0x20000000 0x424000>;
};
};
pwm0: pwm@10015000 {
compatible = "sifive,pwm0";
sifive,comparator-widthbits = <8>;
sifive,ncomparators = <4>;
interrupt-parent = <&plic>;
interrupts = <40 41 42 43>;
reg = <0x10015000 0x1000>;
reg-names = "control";
clocks = <&hfclk>;
pinmux = <&gpio0 0x0F 0x0F>;
};
i2c0: i2c@10016000 {
compatible = "sifive,i2c0";
interrupt-parent = <&plic>;
interrupts = <52>;
reg = <0x10016000 0x1000>;
reg-names = "control";
clocks = <&hfclk>;
pinmux = <&gpio0 0x0 0x3000>;
};
uart1: serial@10023000 {
compatible = "sifive,uart0";
interrupt-parent = <&plic>;
interrupts = <4>;
reg = <0x10023000 0x1000>;
reg-names = "control";
clocks = <&hfclk>;
pinmux = <&gpio0 0x0 0x840000>;
};
spi1: spi@10024000 {
compatible = "sifive,spi0";
interrupt-parent = <&plic>;
interrupts = <6>;
reg = <0x10024000 0x1000>;
reg-names = "control";
clocks = <&hfclk>;
pinmux = <&gpio0 0x0 0x0003C>;
};
pwm1: pwm@10025000 {
compatible = "sifive,pwm0";
sifive,comparator-widthbits = <16>;
sifive,ncomparators = <4>;
interrupt-parent = <&plic>;
interrupts = <44 45 46 47>;
reg = <0x10025000 0x1000>;
reg-names = "control";
clocks = <&hfclk>;
pinmux = <&gpio0 0x780000 0x780000>;
};
spi2: spi@10034000 {
compatible = "sifive,spi0";
interrupt-parent = <&plic>;
interrupts = <7>;
reg = <0x10034000 0x1000>;
reg-names = "control";
clocks = <&hfclk>;
pinmux = <&gpio0 0x0 0xFC000000>;
};
pwm2: pwm@10035000 {
compatible = "sifive,pwm0";
sifive,comparator-widthbits = <16>;
sifive,ncomparators = <4>;
interrupt-parent = <&plic>;
interrupts = <48 49 50 51>;
reg = <0x10035000 0x1000>;
reg-names = "control";
clocks = <&hfclk>;
pinmux = <&gpio0 0x3C00 0x3C00>;
};
dtim: dtim@80000000 {
compatible = "sifive,dtim0";
reg = <0x80000000 0x4000>;
reg-names = "mem";
};
};
};
10 changes: 10 additions & 0 deletions bsp/sparkfun-redv/design.dts
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/include/ "core.dts"
/ {
chosen {
metal,entry = <&spi0 1 65536>;
metal,boothart = <&L6>;
stdout-path = "/soc/serial@10013000:115200";
metal,itim = <&itim 0 0>;
metal,ram = <&dtim 0 0>;
};
};
54 changes: 54 additions & 0 deletions bsp/sparkfun-redv/design.reglist
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zero
ra
sp
gp
tp
t0
t1
t2
fp
s1
a0
a1
a2
a3
a4
a5
a6
a7
s2
s3
s4
s5
s6
s7
s8
s9
s10
s11
t3
t4
t5
t6
pc
mstatus
misa
mie
mtvec
mscratch
mepc
mcause
mtval
mip
mvendorid
marchid
mimpid
mhartid
tselect
tdata1
tdata2
tdata3
dcsr
dpc
dscratch
priv
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