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s390: Superword Level Parallelization with Vector
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@sid8606
sid8606 committed Feb 9, 2024
1 parent 76afa02 commit cdf16be
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Showing 16 changed files with 1,057 additions and 62 deletions.
49 changes: 45 additions & 4 deletions src/hotspot/cpu/s390/assembler_s390.hpp
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Original file line number Diff line number Diff line change
Expand Up @@ -1238,6 +1238,9 @@ class Assembler : public AbstractAssembler {
// NOR
#define VNO_ZOPC (unsigned long)(0xe7L << 40 | 0x6bL << 0) // V1 := !(V2 | V3), element size = 2**m

//NOT-XOR
#define VNX_ZOPC (unsigned long)(0xe7L << 40 | 0x6cL << 0) // V1 := !(V2 | V3), element size = 2**m

// OR
#define VO_ZOPC (unsigned long)(0xe7L << 40 | 0x6aL << 0) // V1 := V2 | V3, element size = 2**m

Expand Down Expand Up @@ -1289,6 +1292,12 @@ class Assembler : public AbstractAssembler {
#define VSTRC_ZOPC (unsigned long)(0xe7L << 40 | 0x8aL << 0) // String range compare
#define VISTR_ZOPC (unsigned long)(0xe7L << 40 | 0x5cL << 0) // Isolate String

#define VFA_ZOPC (unsigned long)(0xe7L << 40 | 0xE3L << 0) // V1 := V2 + V3, element size = 2**m
#define VFS_ZOPC (unsigned long)(0xe7L << 40 | 0xE2L << 0) // V1 := V2 - V3, element size = 2**m
#define VFM_ZOPC (unsigned long)(0xe7L << 40 | 0xE7L << 0) // V1 := V2 * V3, element size = 2**m
#define VFD_ZOPC (unsigned long)(0xe7L << 40 | 0xE5L << 0) // V1 := V2 / V3, element size = 2**m
#define VFSQ_ZOPC (unsigned long)(0xe7L << 40 | 0xCEL << 0) // V1 := sqrt of V2, element size = 2**m


//--------------------------------
//-- Miscellaneous Operations --
Expand Down Expand Up @@ -2485,6 +2494,7 @@ class Assembler : public AbstractAssembler {
inline void z_vleh( VectorRegister v1, int64_t d2, Register x2, Register b2, int64_t m3);
inline void z_vlef( VectorRegister v1, int64_t d2, Register x2, Register b2, int64_t m3);
inline void z_vleg( VectorRegister v1, int64_t d2, Register x2, Register b2, int64_t m3);
inline void z_vl(VectorRegister v1, const Address& a);

// Gather/Scatter
inline void z_vgef( VectorRegister v1, int64_t d2, VectorRegister vx2, Register b2, int64_t m3);
Expand Down Expand Up @@ -2519,10 +2529,10 @@ class Assembler : public AbstractAssembler {
inline void z_vlgvg( Register r1, VectorRegister v3, int64_t d2, Register b2);

inline void z_vlvg( VectorRegister v1, Register r3, int64_t d2, Register b2, int64_t m4);
inline void z_vlvgb( VectorRegister v1, Register r3, int64_t d2, Register b2);
inline void z_vlvgh( VectorRegister v1, Register r3, int64_t d2, Register b2);
inline void z_vlvgf( VectorRegister v1, Register r3, int64_t d2, Register b2);
inline void z_vlvgg( VectorRegister v1, Register r3, int64_t d2, Register b2);
inline void z_vlvgb( VectorRegister v1, Register r3, int64_t d2, Register b2=Z_R0);
inline void z_vlvgh( VectorRegister v1, Register r3, int64_t d2, Register b2=Z_R0);
inline void z_vlvgf( VectorRegister v1, Register r3, int64_t d2, Register b2=Z_R0);
inline void z_vlvgg( VectorRegister v1, Register r3, int64_t d2, Register b2=Z_R0);

inline void z_vlvgp( VectorRegister v1, Register r2, Register r3);

Expand Down Expand Up @@ -2614,6 +2624,7 @@ class Assembler : public AbstractAssembler {
inline void z_vstef( VectorRegister v1, int64_t d2, Register x2, Register b2, int64_t m3);
inline void z_vsteg( VectorRegister v1, int64_t d2, Register x2, Register b2, int64_t m3);
inline void z_vstl( VectorRegister v1, Register r3, int64_t d2, Register b2);
inline void z_vst(VectorRegister v1, const Address& a);

// Misc
inline void z_vgm( VectorRegister v1, int64_t imm2, int64_t imm3, int64_t m4);
Expand Down Expand Up @@ -2670,6 +2681,9 @@ class Assembler : public AbstractAssembler {

// MULTIPLY
inline void z_vml( VectorRegister v1, VectorRegister v2, VectorRegister v3, int64_t m4);
inline void z_vmlb( VectorRegister v1, VectorRegister v2, VectorRegister v3);
inline void z_vmlhw( VectorRegister v1, VectorRegister v2, VectorRegister v3);
inline void z_vmlf( VectorRegister v1, VectorRegister v2, VectorRegister v3);
inline void z_vmh( VectorRegister v1, VectorRegister v2, VectorRegister v3, int64_t m4);
inline void z_vmlh( VectorRegister v1, VectorRegister v2, VectorRegister v3, int64_t m4);
inline void z_vme( VectorRegister v1, VectorRegister v2, VectorRegister v3, int64_t m4);
Expand Down Expand Up @@ -2734,6 +2748,9 @@ class Assembler : public AbstractAssembler {
// NOR
inline void z_vno( VectorRegister v1, VectorRegister v2, VectorRegister v3);

//NOT-XOR
inline void z_vnx( VectorRegister v1, VectorRegister v2, VectorRegister v3);

// OR
inline void z_vo( VectorRegister v1, VectorRegister v2, VectorRegister v3);

Expand Down Expand Up @@ -2890,6 +2907,30 @@ class Assembler : public AbstractAssembler {

// Floatingpoint instructions
// ==========================
// Add
inline void z_vfa(VectorRegister v1, VectorRegister v2, VectorRegister v3, int64_t m4);
inline void z_vfasb(VectorRegister v1, VectorRegister v2, VectorRegister v3);
inline void z_vfadb(VectorRegister v1, VectorRegister v2, VectorRegister v3);

//SUB
inline void z_vfs(VectorRegister v1, VectorRegister v2, VectorRegister v3, int64_t m4);
inline void z_vfssb(VectorRegister v1, VectorRegister v2, VectorRegister v3);
inline void z_vfsdb(VectorRegister v1, VectorRegister v2, VectorRegister v3);

//MUL
inline void z_vfm(VectorRegister v1, VectorRegister v2, VectorRegister v3, int64_t m4);
inline void z_vfmsb(VectorRegister v1, VectorRegister v2, VectorRegister v3);
inline void z_vfmdb(VectorRegister v1, VectorRegister v2, VectorRegister v3);

//DIV
inline void z_vfd(VectorRegister v1, VectorRegister v2, VectorRegister v3, int64_t m4);
inline void z_vfdsb(VectorRegister v1, VectorRegister v2, VectorRegister v3);
inline void z_vfddb(VectorRegister v1, VectorRegister v2, VectorRegister v3);

//square root
inline void z_vfsq(VectorRegister v1, VectorRegister v2, int64_t m3);
inline void z_vfsqsb(VectorRegister v1, VectorRegister v2);
inline void z_vfsqdb(VectorRegister v1, VectorRegister v2);

// compare instructions
inline void z_cebr(FloatRegister r1, FloatRegister r2); // compare (r1, r2) ; float
Expand Down
43 changes: 40 additions & 3 deletions src/hotspot/cpu/s390/assembler_s390.inline.hpp
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Original file line number Diff line number Diff line change
Expand Up @@ -778,6 +778,7 @@ inline void Assembler::z_vleb( VectorRegister v1, int64_t d2, Register x2, Reg
inline void Assembler::z_vleh( VectorRegister v1, int64_t d2, Register x2, Register b2, int64_t ix3){emit_48(VLEH_ZOPC | vreg(v1, 8) | rxmask_48(d2, x2, b2) | uimm4(ix3, 32, 48)); }
inline void Assembler::z_vlef( VectorRegister v1, int64_t d2, Register x2, Register b2, int64_t ix3){emit_48(VLEF_ZOPC | vreg(v1, 8) | rxmask_48(d2, x2, b2) | uimm4(ix3, 32, 48)); }
inline void Assembler::z_vleg( VectorRegister v1, int64_t d2, Register x2, Register b2, int64_t ix3){emit_48(VLEG_ZOPC | vreg(v1, 8) | rxmask_48(d2, x2, b2) | uimm4(ix3, 32, 48)); }
inline void Assembler::z_vl(VectorRegister v1, const Address& a) { z_vl(v1, a.disp(), a.indexOrR0(), a.baseOrR0()); }

// Gather/Scatter
inline void Assembler::z_vgef( VectorRegister v1, int64_t d2, VectorRegister vx2, Register b2, int64_t ix3) {emit_48(VGEF_ZOPC | vreg(v1, 8) | rvmask_48(d2, vx2, b2) | uimm4(ix3, 32, 48)); }
Expand Down Expand Up @@ -811,7 +812,7 @@ inline void Assembler::z_vlgvh( Register r1, VectorRegister v3, int64_t d2, Reg
inline void Assembler::z_vlgvf( Register r1, VectorRegister v3, int64_t d2, Register b2) {z_vlgv(r1, v3, d2, b2, VRET_FW); } // load FW from VR element (index d2(b2)) into GR (logical)
inline void Assembler::z_vlgvg( Register r1, VectorRegister v3, int64_t d2, Register b2) {z_vlgv(r1, v3, d2, b2, VRET_DW); } // load DW from VR element (index d2(b2)) into GR.

inline void Assembler::z_vlvg( VectorRegister v1, Register r3, int64_t d2, Register b2, int64_t m4) {emit_48(VLVG_ZOPC | vreg(v1, 8) | reg(r3, 12, 48) | rsmask_48(d2, b2) | vesc_mask(m4, VRET_BYTE, VRET_DW, 32)); }
inline void Assembler::z_vlvg( VectorRegister v1, Register r3, int64_t d2, Register b2, int64_t m4) {emit_48(VLVG_ZOPC | vreg(v1, 8) | reg(r3, 12, 48) | rsmaskt_32(d2, b2) | vesc_mask(m4, VRET_BYTE, VRET_DW, 32)); }
inline void Assembler::z_vlvgb( VectorRegister v1, Register r3, int64_t d2, Register b2) {z_vlvg(v1, r3, d2, b2, VRET_BYTE); }
inline void Assembler::z_vlvgh( VectorRegister v1, Register r3, int64_t d2, Register b2) {z_vlvg(v1, r3, d2, b2, VRET_HW); }
inline void Assembler::z_vlvgf( VectorRegister v1, Register r3, int64_t d2, Register b2) {z_vlvg(v1, r3, d2, b2, VRET_FW); }
Expand Down Expand Up @@ -907,6 +908,7 @@ inline void Assembler::z_vsteh( VectorRegister v1, int64_t d2, Register x2, Reg
inline void Assembler::z_vstef( VectorRegister v1, int64_t d2, Register x2, Register b2, int64_t ix3){emit_48(VSTEF_ZOPC | vreg(v1, 8) | rxmask_48(d2, x2, b2) | uimm4(ix3, 32, 48)); }
inline void Assembler::z_vsteg( VectorRegister v1, int64_t d2, Register x2, Register b2, int64_t ix3){emit_48(VSTEG_ZOPC | vreg(v1, 8) | rxmask_48(d2, x2, b2) | uimm4(ix3, 32, 48)); }
inline void Assembler::z_vstl( VectorRegister v1, Register r3, int64_t d2, Register b2) {emit_48(VSTL_ZOPC | vreg(v1, 8) | reg(r3, 12, 48) | rsmask_48(d2, b2)); }
inline void Assembler::z_vst(VectorRegister v1, const Address& a) { z_vst(v1, a.disp(), a.indexOrR0(), a.baseOrR0()); }

// Misc
inline void Assembler::z_vgm( VectorRegister v1, int64_t imm2, int64_t imm3, int64_t m4) {emit_48(VGM_ZOPC | vreg(v1, 8) | uimm8( imm2, 16, 48) | uimm8(imm3, 24, 48) | vesc_mask(m4, VRET_BYTE, VRET_DW, 32)); }
Expand Down Expand Up @@ -946,6 +948,8 @@ inline void Assembler::z_vacch( VectorRegister v1, VectorRegister v2, VectorReg
inline void Assembler::z_vaccf( VectorRegister v1, VectorRegister v2, VectorRegister v3) {z_vacc(v1, v2, v3, VRET_FW); } // vector element type 'F'
inline void Assembler::z_vaccg( VectorRegister v1, VectorRegister v2, VectorRegister v3) {z_vacc(v1, v2, v3, VRET_DW); } // vector element type 'G'
inline void Assembler::z_vaccq( VectorRegister v1, VectorRegister v2, VectorRegister v3) {z_vacc(v1, v2, v3, VRET_QW); } // vector element type 'Q'
//


// SUB
inline void Assembler::z_vs( VectorRegister v1, VectorRegister v2, VectorRegister v3, int64_t m4) {emit_48(VS_ZOPC | vreg(v1, 8) | vreg(v2, 12) | vreg(v3, 16) | vesc_mask(m4, VRET_BYTE, VRET_QW, 32)); }
Expand All @@ -964,6 +968,9 @@ inline void Assembler::z_vscbiq( VectorRegister v1, VectorRegister v2, VectorReg
// MULTIPLY
inline void Assembler::z_vml( VectorRegister v1, VectorRegister v2, VectorRegister v3, int64_t m4) {emit_48(VML_ZOPC | vreg(v1, 8) | vreg(v2, 12) | vreg(v3, 16) | vesc_mask(m4, VRET_BYTE, VRET_FW, 32)); }
inline void Assembler::z_vmh( VectorRegister v1, VectorRegister v2, VectorRegister v3, int64_t m4) {emit_48(VMH_ZOPC | vreg(v1, 8) | vreg(v2, 12) | vreg(v3, 16) | vesc_mask(m4, VRET_BYTE, VRET_FW, 32)); }
inline void Assembler::z_vmlb( VectorRegister v1, VectorRegister v2, VectorRegister v3) {z_vml(v1, v2, v3, VRET_BYTE);} // vector element type 'B'
inline void Assembler::z_vmlhw( VectorRegister v1, VectorRegister v2, VectorRegister v3) {z_vml(v1, v2, v3, VRET_HW);} // vector element type 'H'
inline void Assembler::z_vmlf( VectorRegister v1, VectorRegister v2, VectorRegister v3) {z_vml(v1, v2, v3, VRET_FW);} // vector element type 'F'
inline void Assembler::z_vmlh( VectorRegister v1, VectorRegister v2, VectorRegister v3, int64_t m4) {emit_48(VMLH_ZOPC | vreg(v1, 8) | vreg(v2, 12) | vreg(v3, 16) | vesc_mask(m4, VRET_BYTE, VRET_FW, 32)); }
inline void Assembler::z_vme( VectorRegister v1, VectorRegister v2, VectorRegister v3, int64_t m4) {emit_48(VME_ZOPC | vreg(v1, 8) | vreg(v2, 12) | vreg(v3, 16) | vesc_mask(m4, VRET_BYTE, VRET_FW, 32)); }
inline void Assembler::z_vmle( VectorRegister v1, VectorRegister v2, VectorRegister v3, int64_t m4) {emit_48(VMLE_ZOPC | vreg(v1, 8) | vreg(v2, 12) | vreg(v3, 16) | vesc_mask(m4, VRET_BYTE, VRET_FW, 32)); }
Expand Down Expand Up @@ -1026,6 +1033,9 @@ inline void Assembler::z_vx( VectorRegister v1, VectorRegister v2, VectorReg
// NOR
inline void Assembler::z_vno( VectorRegister v1, VectorRegister v2, VectorRegister v3) {emit_48(VNO_ZOPC | vreg(v1, 8) | vreg(v2, 12) | vreg(v3, 16)); }

//NOT-XOR
inline void Assembler::z_vnx( VectorRegister v1, VectorRegister v2, VectorRegister v3) {emit_48(VNX_ZOPC | vreg(v1, 8) | vreg(v2, 12) | vreg(v3, 16)); }

// OR
inline void Assembler::z_vo( VectorRegister v1, VectorRegister v2, VectorRegister v3) {emit_48(VO_ZOPC | vreg(v1, 8) | vreg(v2, 12) | vreg(v3, 16)); }

Expand Down Expand Up @@ -1179,12 +1189,39 @@ inline void Assembler::z_vistrbs(VectorRegister v1, VectorRegister v2)
inline void Assembler::z_vistrhs(VectorRegister v1, VectorRegister v2) {z_vistr(v1, v2, VRET_HW, VOPRC_CCSET); }
inline void Assembler::z_vistrfs(VectorRegister v1, VectorRegister v2) {z_vistr(v1, v2, VRET_FW, VOPRC_CCSET); }


//-------------------------------
// FLOAT INSTRUCTIONS
// Vector FLOAT INSTRUCTIONS
//-------------------------------
//Add
inline void Assembler::z_vfa( VectorRegister v1, VectorRegister v2, VectorRegister v3, int64_t m4) {emit_48(VFA_ZOPC | vreg(v1, 8) | vreg(v2, 12) | vreg(v3, 16) | vesc_mask(m4, VRET_FW, VRET_QW, 32)); }
inline void Assembler::z_vfasb( VectorRegister v1, VectorRegister v2, VectorRegister v3) {z_vfa(v1, v2, v3, VRET_FW); } // vector element type 'F'
inline void Assembler::z_vfadb( VectorRegister v1, VectorRegister v2, VectorRegister v3) {z_vfa(v1, v2, v3, VRET_DW); } // vector element type 'G'

//SUB
//----------------
inline void Assembler::z_vfs( VectorRegister v1, VectorRegister v2, VectorRegister v3, int64_t m4) {emit_48(VFS_ZOPC | vreg(v1, 8) | vreg(v2, 12) | vreg(v3, 16) | vesc_mask(m4, VRET_FW, VRET_QW, 32)); }
inline void Assembler::z_vfssb( VectorRegister v1, VectorRegister v2, VectorRegister v3) {z_vfs(v1, v2, v3, VRET_FW); } // vector element type 'F'
inline void Assembler::z_vfsdb( VectorRegister v1, VectorRegister v2, VectorRegister v3) {z_vfs(v1, v2, v3, VRET_DW); } // vector element type 'G'
//
//MUL
inline void Assembler::z_vfm( VectorRegister v1, VectorRegister v2, VectorRegister v3, int64_t m4) {emit_48(VFM_ZOPC | vreg(v1, 8) | vreg(v2, 12) | vreg(v3, 16) | vesc_mask(m4, VRET_FW, VRET_QW, 32)); }
inline void Assembler::z_vfmsb( VectorRegister v1, VectorRegister v2, VectorRegister v3) {z_vfm(v1, v2, v3, VRET_FW); } // vector element type 'F'
inline void Assembler::z_vfmdb( VectorRegister v1, VectorRegister v2, VectorRegister v3) {z_vfm(v1, v2, v3, VRET_DW); } // vector element type 'G'

//DIV
inline void Assembler::z_vfd( VectorRegister v1, VectorRegister v2, VectorRegister v3, int64_t m4) {emit_48(VFD_ZOPC | vreg(v1, 8) | vreg(v2, 12) | vreg(v3, 16) | vesc_mask(m4, VRET_FW, VRET_QW, 32)); }
inline void Assembler::z_vfdsb( VectorRegister v1, VectorRegister v2, VectorRegister v3) {z_vfd(v1, v2, v3, VRET_FW); } // vector element type 'F'
inline void Assembler::z_vfddb( VectorRegister v1, VectorRegister v2, VectorRegister v3) {z_vfd(v1, v2, v3, VRET_DW); } // vector element type 'G'

// square root
//---------------
inline void Assembler::z_vfsq( VectorRegister v1, VectorRegister v2, int64_t m3) {emit_48(VFSQ_ZOPC | vreg(v1, 8) | vreg(v2, 12) | vesc_mask(m3, VRET_FW, VRET_QW, 32)); }
inline void Assembler::z_vfsqsb( VectorRegister v1, VectorRegister v2) {z_vfsq(v1, v2, VRET_FW); }
inline void Assembler::z_vfsqdb( VectorRegister v1, VectorRegister v2) {z_vfsq(v1, v2, VRET_DW); }

//-------------------------------
// FLOAT INSTRUCTIONS
//-------------------------------
// LOAD
//----------------
inline void Assembler::z_ler( FloatRegister r1, FloatRegister r2) { emit_16( LER_ZOPC | fregt(r1,8,16) | freg(r2,12,16)); }
Expand Down
2 changes: 1 addition & 1 deletion src/hotspot/cpu/s390/c2_globals_s390.hpp
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Original file line number Diff line number Diff line change
Expand Up @@ -60,7 +60,7 @@ define_pd_global(bool, UseCISCSpill, true);
define_pd_global(bool, OptoBundling, false);
define_pd_global(bool, OptoScheduling, false);
define_pd_global(bool, OptoRegScheduling, false);
define_pd_global(bool, SuperWordLoopUnrollAnalysis, false);
define_pd_global(bool, SuperWordLoopUnrollAnalysis, true);
// On s390x, we can clear the array with a single instruction,
// so don't idealize it.
define_pd_global(bool, IdealizeClearArrayNode, false);
Expand Down
3 changes: 3 additions & 0 deletions src/hotspot/cpu/s390/globals_s390.hpp
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Original file line number Diff line number Diff line change
Expand Up @@ -108,6 +108,9 @@ define_pd_global(intx, InitArrayShortSize, 1*BytesPerLong);
/* Seems to pay off with 2 pages already. */ \
product(size_t, MVCLEThreshold, +2*(4*K), DIAGNOSTIC, \
"Threshold above which page-aligned MVCLE copy/init is used.") \
/* special instructions */ \
product(bool, SuperwordUseVX, false, \
"Use Z15 Vector instructions for superword optimization.") \
\
product(bool, PreferLAoverADD, false, DIAGNOSTIC, \
"Use LA/LAY instructions over ADD instructions (z/Architecture).") \
Expand Down
8 changes: 5 additions & 3 deletions src/hotspot/cpu/s390/registerSaver_s390.hpp
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Original file line number Diff line number Diff line change
Expand Up @@ -47,10 +47,10 @@ class RegisterSaver {

// Boolean flags to force only argument registers to be saved.
static int live_reg_save_size(RegisterSet reg_set);
static int live_reg_frame_size(RegisterSet reg_set);
static int live_reg_frame_size(RegisterSet reg_set, bool save_vectors = false);
// Specify the register that should be stored as the return pc in the current frame.
static OopMap* save_live_registers(MacroAssembler* masm, RegisterSet reg_set, Register return_pc = Z_R14);
static void restore_live_registers(MacroAssembler* masm, RegisterSet reg_set);
static OopMap* save_live_registers(MacroAssembler* masm, RegisterSet reg_set, Register return_pc = Z_R14, bool save_vectors = false);
static void restore_live_registers(MacroAssembler* masm, RegisterSet reg_set, bool save_vectors = false);

// Generate the OopMap (again, regs where saved before).
static OopMap* generate_oop_map(MacroAssembler* masm, RegisterSet reg_set);
Expand All @@ -65,11 +65,13 @@ class RegisterSaver {
int_reg = 0,
float_reg = 1,
excluded_reg = 2, // Not saved/restored.
v_reg = 3
} RegisterType;

typedef enum {
reg_size = 8,
half_reg_size = reg_size / 2,
v_reg_size = 16
} RegisterConstants;

// Remember type, number, and VMReg.
Expand Down
13 changes: 7 additions & 6 deletions src/hotspot/cpu/s390/register_s390.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -26,11 +26,6 @@
#include "precompiled.hpp"
#include "register_s390.hpp"


const int ConcreteRegisterImpl::max_gpr = Register::number_of_registers * 2;
const int ConcreteRegisterImpl::max_fpr = ConcreteRegisterImpl::max_gpr +
FloatRegister::number_of_registers * 2;

const char* Register::name() const {
const char* names[number_of_registers] = {
"Z_R0", "Z_R1", "Z_R2", "Z_R3", "Z_R4", "Z_R5", "Z_R6", "Z_R7",
Expand All @@ -54,5 +49,11 @@ const char* VectorRegister::name() const {
"Z_V16", "Z_V17", "Z_V18", "Z_V19", "Z_V20", "Z_V21", "Z_V22", "Z_V23",
"Z_V24", "Z_V25", "Z_V26", "Z_V27", "Z_V28", "Z_V29", "Z_V30", "Z_V31"
};
return is_valid() ? names[encoding()] : "fnoreg";
return is_valid() ? names[encoding()] : "vnoreg";
}

// Method to convert a FloatRegister to a VectorRegister (VectorRegister)
VectorRegister FloatRegister::to_vr() const {
if (*this == fnoreg) { return vnoreg; }
return as_VectorRegister(encoding());
}
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