Address review comments

sid8606 · Mar 15, 2024 · 8bb4bc3 · 8bb4bc3
1 parent 00b90ab
commit 8bb4bc3
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Showing 4 changed files with 11 additions and 20 deletions.
diff --git a/src/hotspot/cpu/s390/assembler_s390.inline.hpp b/src/hotspot/cpu/s390/assembler_s390.inline.hpp
@@ -948,8 +948,6 @@ inline void Assembler::z_vacch(  VectorRegister v1, VectorRegister v2, VectorReg
 inline void Assembler::z_vaccf(  VectorRegister v1, VectorRegister v2, VectorRegister v3)             {z_vacc(v1, v2, v3, VRET_FW); }      // vector element type 'F'
 inline void Assembler::z_vaccg(  VectorRegister v1, VectorRegister v2, VectorRegister v3)             {z_vacc(v1, v2, v3, VRET_DW); }      // vector element type 'G'
 inline void Assembler::z_vaccq(  VectorRegister v1, VectorRegister v2, VectorRegister v3)             {z_vacc(v1, v2, v3, VRET_QW); }      // vector element type 'Q'
-                                                                                                                                           //
-
 
 // SUB
 inline void Assembler::z_vs(     VectorRegister v1, VectorRegister v2, VectorRegister v3, int64_t m4) {emit_48(VS_ZOPC    | vreg(v1,  8) | vreg(v2, 12) | vreg(v3, 16) | vesc_mask(m4, VRET_BYTE, VRET_QW, 32)); }

diff --git a/src/hotspot/cpu/s390/s390.ad b/src/hotspot/cpu/s390/s390.ad
@@ -353,8 +353,6 @@ register %{
 
   reg_def Z_CR(SOC, SOC, Op_RegFlags, 0, Z_CR->as_VMReg());   // volatile
 
-
-
 // Specify priority of register selection within phases of register
 // allocation. Highest priority is first. A useful heuristic is to
 // give registers a low priority when they are required by machine
@@ -756,8 +754,6 @@ reg_class z_v_reg(
 
 %}
 
-
-
 //----------DEFINITION BLOCK---------------------------------------------------
 // Define 'name --> value' mappings to inform the ADLC of an integer valued name.
 // Current support includes integer values in the range [0, 0x7FFFFFFF].
@@ -1206,8 +1202,8 @@ static enum RC rc_class(OptoReg::Name reg) {
   }
 
   // Between float regs & stack are the flags regs.
-  //assert(OptoReg::is_stack(reg) || reg < 64+64+128, "blow up if spilling flags");
-  assert(reg >= OptoReg::stack0(), "blow up if spilling flags");
+  assert(OptoReg::is_stack(reg) || reg < 64+64+128, "blow up if spilling flags");
+  //assert(reg >= OptoReg::stack0(), "blow up if spilling flags");
   return rc_stack;
 }
 
@@ -1292,16 +1288,14 @@ uint MachSpillCopyNode::implementation(CodeBuffer *cbuf, PhaseRegAlloc *ra_, boo
       VectorRegister Rsrc = as_VectorRegister(Matcher::_regEncode[src_lo]);
       if (cbuf) {
         C2_MacroAssembler _masm(cbuf);
-        __ z_vst(Rsrc,
-              Address(Z_SP, 0, dst_offset));
+        __ z_vst(Rsrc, Address(Z_SP, 0, dst_offset));
       }
       size += 6;
       } else if (src_lo_rc == rc_stack && dst_lo_rc == rc_vector) {
       VectorRegister Rdst = as_VectorRegister(Matcher::_regEncode[dst_lo]);
       if (cbuf) {
         C2_MacroAssembler _masm(cbuf);
-        __ z_vl(Rdst,
-              Address(Z_SP, 0, src_offset));
+        __ z_vl(Rdst, Address(Z_SP, 0, src_offset));
       }
       size += 6;
       } else if (src_lo_rc == rc_vector && dst_lo_rc == rc_vector) {
@@ -11182,6 +11176,7 @@ instruct vsub8S_reg(vecX dst, vecX src1, vecX src2) %{
   %}
   ins_pipe(pipe_class_dummy);
 %}
+
 instruct vsub4I_reg(vecX dst, vecX src1, vecX src2) %{
   match(Set dst (SubVI src1 src2));
   predicate(n->as_Vector()->length() == 4);

diff --git a/src/hotspot/cpu/s390/sharedRuntime_s390.cpp b/src/hotspot/cpu/s390/sharedRuntime_s390.cpp
@@ -482,7 +482,9 @@ OopMap* RegisterSaver::generate_oop_map(MacroAssembler* masm, RegisterSet reg_se
     }
     offset += reg_size;
   }
+#ifdef ASSERT
   assert(offset == frame_size_in_bytes, "consistency check");
+#endif
   return map;
 }
 

diff --git a/src/hotspot/cpu/s390/vm_version_s390.cpp b/src/hotspot/cpu/s390/vm_version_s390.cpp
@@ -102,19 +102,15 @@ void VM_Version::initialize() {
     if (FLAG_IS_DEFAULT(SuperwordUseVX)) {
       FLAG_SET_ERGO(SuperwordUseVX, true);
     }
-    if (model_ix > 7 && FLAG_IS_DEFAULT(UseSFPV)) {
-      FLAG_SET_ERGO(UseSFPV, true);
-    } else {
-      if (model_ix == 7 && UseSFPV) {
+    if (model_ix > 7 && FLAG_IS_DEFAULT(UseSFPV) && SuperwordUseVX) {
+        FLAG_SET_ERGO(UseSFPV, true);
+    } else if (model_ix == 7 && UseSFPV) {
         warning("UseSFPV specified, but needs at least Z14.");
         FLAG_SET_DEFAULT(UseSFPV, false);
-      }
     }
-  } else {
-    if (SuperwordUseVX) {
+  } else if (SuperwordUseVX) {
       warning("SuperwordUseVX specified, but needs at least Z13.");
       FLAG_SET_DEFAULT(SuperwordUseVX, false);
-    }
   }
   MaxVectorSize = SuperwordUseVX ? 16 : 8;
 #endif