Merge pull request #2 from sgherbst/v1

Initial PyPI version

.gitignore

@@ -2,4 +2,4 @@
 .DS_Store
 msdsl.egg-info
 __pycache__
-build
+tests/*/build

.travis.yml

@@ -0,0 +1,68 @@
+matrix:
+  include:
+  - os: linux
+    dist: bionic
+    addons:
+      apt:
+        packages:
+        - g++-7
+        - libgmp-dev
+        - libmpfr-dev
+        - libmpc-dev
+        - iverilog
+    env:
+    - CC=gcc-7
+    - CXX=g++-7
+  - os: osx
+    osx_image: xcode10.2
+    addons:
+      homebrew:
+        packages:
+          - icarus-verilog
+
+install:
+# Get conda installer
+- if [[ "$TRAVIS_OS_NAME" == "osx" ]]; then
+    wget https://repo.anaconda.com/miniconda/Miniconda3-latest-MacOSX-x86_64.sh -O miniconda.sh;
+  else
+    wget https://repo.anaconda.com/miniconda/Miniconda3-latest-Linux-x86_64.sh -O miniconda.sh;
+  fi
+
+# Install conda (https://docs.conda.io/projects/conda/en/latest/user-guide/tasks/use-conda-with-travis-ci.html)
+- bash miniconda.sh -b -p $HOME/miniconda
+- source "$HOME/miniconda/etc/profile.d/conda.sh"
+- hash -r
+- conda config --set always_yes yes --set changeps1 no
+- conda update -q conda
+- conda info -a
+
+# create and activate conda environment
+- conda create -q -n test-env python=3.7.3
+- conda activate test-env
+
+# install pip so that we can install other packages
+- conda install pip
+
+# speed up the build process until it's fixed at z3
+# see https://github.com/Z3Prover/z3/issues/2800
+- |
+  if [[ "$TRAVIS_OS_NAME" == "osx" ]]; then
+    pip install https://github.com/Z3Prover/z3/releases/download/Nightly/z3_solver-4.8.8.0-py2.py3-none-macosx_10_14_x86_64.whl
+  fi
+
+# install various python dependencies
+- pip install pytest mantle fault pytest-cov
+
+# install svreal
+- git clone https://github.com/sgherbst/svreal.git
+- cd svreal
+- git checkout v1
+- pip install -e .
+- cd ..
+
+# install msdsl
+- pip install -e .
+
+script:
+- pytest --cov-report=xml --cov=msdsl tests/ -v -r s
+- bash <(curl -s https://codecov.io/bash)

MANIFEST.in

@@ -0,0 +1 @@
+include msdsl/msdsl.sv

README.md

@@ -1,17 +1,14 @@
-**NOTE**: Please check out the **v1** branch for the latest work.  These updates will be merged into the master branch soon, coinciding with a release on PyPI.
+# msdsl
+[![Travis Status](https://travis-ci.com/sgherbst/msdsl.svg?branch=master)](https://travis-ci.com/sgherbst/msdsl)
+[![Code Coverage](https://codecov.io/gh/sgherbst/msdsl/branch/master/graph/badge.svg)](https://codecov.io/gh/sgherbst/msdsl)
+[![License: MIT](https://img.shields.io/badge/License-MIT-yellow.svg)](https://opensource.org/licenses/MIT)
 
----
-
-# Introduction
-
-**msdsl** is a Python3 package for generating synthesizable real number models (RNMs) from analog circuits.  
+**msdsl** is a tool for generating synthesizable real number models (RNMs) from analog circuits for use in FPGA emulation. 
 
 # Installation
 
-1. Open a terminal, and note the current directory, since the **pip** command below will clone some code from GitHub and place it in a subdirectory called **src**.  If you prefer to place the cloned code in a different directory, you can specify that by providing the **--src** flag to **pip**.
-2. Install **msdsl** with **pip**:
 ```shell
-> pip install -e git+https://github.com/sgherbst/msdsl.git#egg=msdsl
+> pip install msdsl
 ```
 
 If you get a permissions error when running the **pip** command, you can try adding the **--user** flag.  This will cause **pip** to install packages in your user directory rather than to a system-wide location.

msdsl/__init__.py

@@ -1,8 +1,9 @@
+from .files import get_msdsl_header
 from .expr.svreal import RangeOf
 from .expr.signals import AnalogSignal, DigitalOutput, DigitalInput, AnalogInput, AnalogOutput, DigitalSignal
 from .expr.simplify import distribute_mult
 from .model import MixedSignalModel
 from .generator.verilog import VerilogGenerator
 from .eqn.deriv import Deriv
 from .eqn.cases import eqn_case
-from .expr.expr import to_real, to_sint, to_uint, min_op, max_op, sum_op
+from .expr.expr import to_real, to_sint, to_uint, min_op, max_op, sum_op

msdsl/files.py

@@ -0,0 +1,6 @@
+from pathlib import Path
+
+PACK_DIR = Path(__file__).resolve().parent
+
+def get_msdsl_header():
+    return PACK_DIR / 'msdsl.sv'

msdsl/generator/verilog.py

@@ -148,7 +148,7 @@ def make_mem(self, next_: Signal, curr: Signal, init: Number=0, clk: Signal=None
 
         # create memory for real number
         if isinstance(next_.format_, RealFormat) and isinstance(curr.format_, RealFormat):
-            self.macro_call('MEM_INTO_ANALOG', next_.name, curr.name, ce_name, clk_name, rst_name, str(init))
+            self.macro_call('DFF_INTO_REAL', next_.name, curr.name, rst_name, clk_name, ce_name, str(init))
         # create memory for integer
         elif (isinstance(next_.format_, SIntFormat) and isinstance(curr.format_, SIntFormat)) or \
              (isinstance(next_.format_, UIntFormat) and isinstance(curr.format_, UIntFormat)):
@@ -481,9 +481,7 @@ def init_file(self):
         self.writeln()
 
         # include required libraries
-        self.include('real.sv')
-        self.include('math.sv')
-        self.include('msdsl.sv')
+        self.include('svreal.sv')
         self.writeln()
 
     def include(self, file):