v0.1.3

plugin/msdsl.py → msdsl/plugin/msdsl.py

@@ -1,9 +1,16 @@
 import os
+from pathlib import Path
+from argparse import ArgumentParser
+
+from svreal import get_svreal_header
+
+# path to the top-level msdsl package directory
+PACK_DIR = Path(__file__).resolve().parent.parent
 
+# TODO: figure out how to remove dependency on anasymod (which itself depends on msdsl)
 from anasymod.sources import VerilogHeader, VerilogSource
 from anasymod.defines import Define
-from anasymod.files import mkdir_p, rm_rf, get_from_module, which
-from argparse import ArgumentParser
+from anasymod.files import mkdir_p, rm_rf, which
 from anasymod.util import call
 from anasymod.plugins import Plugin
 from anasymod.config import EmuConfig
@@ -78,11 +85,8 @@ def _setup_sources(self):
         """
 
         # Add MSDSL and SVREAL sources
-        self.add_source(source=VerilogSource(files=get_from_module('msdsl', 'src', '*.sv'), config_path=self._srccfg_path))
-        self.add_source(source=VerilogHeader(files=get_from_module('msdsl', 'include', '*.sv'), config_path=self._srccfg_path))
-
-        self.add_source(source=VerilogSource(files=get_from_module('svreal', 'src', '*.sv'), config_path=self._srccfg_path))
-        self.add_source(source=VerilogHeader(files=get_from_module('svreal', 'include', '*.sv'), config_path=self._srccfg_path))
+        self.add_source(source=VerilogHeader(files=[PACK_DIR / 'msdsl.sv'], config_path=self._srccfg_path))
+        self.add_source(source=VerilogHeader(files=[get_svreal_header()], config_path=self._srccfg_path))
 
         # Add model sources
         self.add_source(source=VerilogSource(files=os.path.join(self.cfg.model_dir, '*.sv'), config_path=self._srccfg_path))

setup.py

@@ -1,7 +1,7 @@
 from setuptools import setup, find_packages
 
 name = 'msdsl'
-version = '0.1.2'
+version = '0.1.3'
 
 DESCRIPTION = '''\
 Library for generating synthesizable mixed-signal models for FPGA emulation\
@@ -21,8 +21,6 @@
                 'model', 'models', 'generator', 'verilog', 'system-verilog',
                 'system verilog', 'synthesizable', 'emulation', 'fpga'],
     packages=find_packages(),
-    scripts=[
-    ],
     install_requires=[
         'svreal',
         'scipy',