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Cheshire (Digilent Genesys2) support #188

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merged 1 commit into from
Feb 4, 2025
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omeh-a
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@omeh-a omeh-a commented Nov 25, 2024

This PR adds support for the Cheshire RISC-V APU design on the Digilent Genesys 2 board. See seL4/seL4#1354 for more information.

@omeh-a omeh-a marked this pull request as draft January 17, 2025 07:06
@omeh-a omeh-a marked this pull request as ready for review January 23, 2025 00:47
@omeh-a omeh-a force-pushed the cheshire branch 2 times, most recently from d15e81e to cbbfb74 Compare January 23, 2025 00:51
@omeh-a omeh-a force-pushed the cheshire branch 2 times, most recently from b99efe5 to 4784dbc Compare February 4, 2025 05:14
@Ivan-Velickovic
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Gitlint still complaining, can't merge without that fixed.

Added support for Cheshire (CVA6). Refactored Ariane and Cheshire to
use a shared mach definition since they both implement the CVA6 core
and have common code.

Signed-off-by: Matt Rossouw <[email protected]>
@Ivan-Velickovic Ivan-Velickovic merged commit a334419 into seL4:master Feb 4, 2025
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2 participants