PolarFire SoC: Initial Support

Disable huge page Turn timer tests off for the Polarfire platform Signed-off-by: Jesse Millwood <[email protected]>
seL4 · Sep 23, 2020 · 24c3369 · 24c3369
1 parent ffefb10
commit 24c3369
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Showing 2 changed files with 9 additions and 2 deletions.
diff --git a/apps/sel4test-tests/arch/riscv/arch_frame_type.h b/apps/sel4test-tests/arch/riscv/arch_frame_type.h
@@ -18,7 +18,8 @@
 /* This list must be ordered by size - highest first */
 static const frame_type_t frame_types[] = {
     /* Rocket-Chip for zedboard only has 256MiB of RAM, so we can't allocate a 1GiB page */
-#if __riscv_xlen == 64 && !defined(CONFIG_BUILD_ROCKET_CHIP_ZEDBOARD) && !defined(CONFIG_PLAT_ARIANE)
+    /* Polarfire has 1GiB of memory can't allocate a 1GiB page for user space */
+#if __riscv_xlen == 64 && !defined(CONFIG_BUILD_ROCKET_CHIP_ZEDBOARD) && !defined(CONFIG_PLAT_ARIANE) &&!defined(CONFIG_PLAT_POLARFIRE)
     { seL4_RISCV_Giga_Page, 0, seL4_HugePageBits, },
 #endif
     { seL4_RISCV_Mega_Page, 0, seL4_LargePageBits, },

diff --git a/settings.cmake b/settings.cmake
@@ -80,7 +80,13 @@ if(NOT Sel4testAllowSettingsOverride)
         else()
             set(Sel4testHaveTimer OFF CACHE BOOL "" FORCE)
         endif()
-    elseif(KernelPlatformZynqmp OR (SIMULATION AND (KernelArchRiscV OR KernelArchARM)))
+    elseif(
+        KernelPlatformZynqmp
+        OR KernelPlatformPolarfire
+        OR (SIMULATION AND (KernelArchRiscV OR KernelArchARM))
+    )
+        # Frequency settings of the ZynqMP make the ltimer tests problematic
+        # Polarfire does not have a complete ltimer implementation
         set(Sel4testHaveTimer OFF CACHE BOOL "" FORCE)
     else()
         set(Sel4testHaveTimer ON CACHE BOOL "" FORCE)