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Remove metadata from target specs
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This metadata was leftover from the builtin targets they are based on.

Signed-off-by: Nick Spinale <[email protected]>
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nspin committed Sep 19, 2024
1 parent 5f6d5da commit a49e59d
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Showing 31 changed files with 148 additions and 105 deletions.
1 change: 1 addition & 0 deletions Cargo.lock

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3 changes: 3 additions & 0 deletions crates/sel4-generate-target-specs/Cargo.nix
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Expand Up @@ -11,4 +11,7 @@ mk {
dependencies = {
inherit (versions) serde_json clap;
};
build-dependencies = {
inherit (versions) rustc_version;
};
}
3 changes: 3 additions & 0 deletions crates/sel4-generate-target-specs/Cargo.toml
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Expand Up @@ -19,3 +19,6 @@ license = "BSD-2-Clause"
[dependencies]
clap = "4.4.6"
serde_json = "1.0.87"

[build-dependencies]
rustc_version = "0.4.0"
31 changes: 31 additions & 0 deletions crates/sel4-generate-target-specs/build.rs
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@@ -0,0 +1,31 @@
//
// Copyright 2024, Colias Group, LLC
//
// SPDX-License-Identifier: BSD-2-Clause
//

use core::cmp::Reverse;

// Determine whether rustc includes https://github.com/rust-lang/rust/pull/122305

fn main() {
let key = {
let version_meta = rustc_version::version_meta().unwrap();
let semver = version_meta.semver;
let commit_date = order_date(version_meta.commit_date);
(semver.major, semver.minor, semver.patch, commit_date)
};
let check_cfg_required = (1, 80, 0, order_date(Some("2024-05-05".to_owned())));
let target_spec_has_metadata = (1, 78, 0, order_date(Some("2024-03-15".to_owned())));
if key >= check_cfg_required {
println!("cargo:rustc-check-cfg=cfg(target_spec_has_metadata)");
}
if key >= target_spec_has_metadata {
println!("cargo:rustc-cfg=target_spec_has_metadata");
}
}

// no build date means more recent
fn order_date(date: Option<String>) -> Reverse<Option<Reverse<String>>> {
Reverse(date.map(Reverse))
}
7 changes: 6 additions & 1 deletion crates/sel4-generate-target-specs/src/main.rs
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Expand Up @@ -223,7 +223,12 @@ impl Context {
}

fn builtin(triple: &str) -> Target {
Target::expect_builtin(&TargetTriple::from_triple(triple))
let mut target = Target::expect_builtin(&TargetTriple::from_triple(triple));
#[cfg(target_spec_has_metadata)]
{
target.metadata = Default::default();
}
target
}

fn all_target_specs() -> BTreeMap<String, Target> {
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8 changes: 4 additions & 4 deletions support/targets/aarch64-sel4-microkit-minimal.json
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Expand Up @@ -13,10 +13,10 @@
"llvm-target": "aarch64-unknown-none",
"max-atomic-width": 128,
"metadata": {
"description": "Bare ARM64, hardfloat",
"host_tools": false,
"std": false,
"tier": 2
"description": null,
"host_tools": null,
"std": null,
"tier": null
},
"panic-strategy": "abort",
"pre-link-args": {
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8 changes: 4 additions & 4 deletions support/targets/aarch64-sel4-microkit-resettable-minimal.json
Original file line number Diff line number Diff line change
Expand Up @@ -13,10 +13,10 @@
"llvm-target": "aarch64-unknown-none",
"max-atomic-width": 128,
"metadata": {
"description": "Bare ARM64, hardfloat",
"host_tools": false,
"std": false,
"tier": 2
"description": null,
"host_tools": null,
"std": null,
"tier": null
},
"panic-strategy": "abort",
"pre-link-args": {
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8 changes: 4 additions & 4 deletions support/targets/aarch64-sel4-microkit-resettable.json
Original file line number Diff line number Diff line change
Expand Up @@ -13,10 +13,10 @@
"llvm-target": "aarch64-unknown-none",
"max-atomic-width": 128,
"metadata": {
"description": "Bare ARM64, hardfloat",
"host_tools": false,
"std": false,
"tier": 2
"description": null,
"host_tools": null,
"std": null,
"tier": null
},
"pre-link-args": {
"gnu-lld": [
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8 changes: 4 additions & 4 deletions support/targets/aarch64-sel4-microkit.json
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Expand Up @@ -13,10 +13,10 @@
"llvm-target": "aarch64-unknown-none",
"max-atomic-width": 128,
"metadata": {
"description": "Bare ARM64, hardfloat",
"host_tools": false,
"std": false,
"tier": 2
"description": null,
"host_tools": null,
"std": null,
"tier": null
},
"pre-link-args": {
"gnu-lld": [
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8 changes: 4 additions & 4 deletions support/targets/aarch64-sel4-minimal.json
Original file line number Diff line number Diff line change
Expand Up @@ -12,10 +12,10 @@
"llvm-target": "aarch64-unknown-none",
"max-atomic-width": 128,
"metadata": {
"description": "Bare ARM64, hardfloat",
"host_tools": false,
"std": false,
"tier": 2
"description": null,
"host_tools": null,
"std": null,
"tier": null
},
"panic-strategy": "abort",
"pre-link-args": {
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8 changes: 4 additions & 4 deletions support/targets/aarch64-sel4.json
Original file line number Diff line number Diff line change
Expand Up @@ -12,10 +12,10 @@
"llvm-target": "aarch64-unknown-none",
"max-atomic-width": 128,
"metadata": {
"description": "Bare ARM64, hardfloat",
"host_tools": false,
"std": false,
"tier": 2
"description": null,
"host_tools": null,
"std": null,
"tier": null
},
"pre-link-args": {
"gnu-lld": [
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8 changes: 4 additions & 4 deletions support/targets/armv7a-sel4-minimal.json
Original file line number Diff line number Diff line change
Expand Up @@ -15,10 +15,10 @@
"llvm-target": "armv7a-none-eabi",
"max-atomic-width": 64,
"metadata": {
"description": "Bare Armv7-A",
"host_tools": false,
"std": false,
"tier": 2
"description": null,
"host_tools": null,
"std": null,
"tier": null
},
"panic-strategy": "abort",
"relocation-model": "static",
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8 changes: 4 additions & 4 deletions support/targets/armv7a-sel4.json
Original file line number Diff line number Diff line change
Expand Up @@ -15,10 +15,10 @@
"llvm-target": "armv7a-none-eabi",
"max-atomic-width": 64,
"metadata": {
"description": "Bare Armv7-A",
"host_tools": false,
"std": false,
"tier": 2
"description": null,
"host_tools": null,
"std": null,
"tier": null
},
"panic-strategy": "abort",
"relocation-model": "static",
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8 changes: 4 additions & 4 deletions support/targets/riscv32imac-sel4-minimal.json
Original file line number Diff line number Diff line change
Expand Up @@ -13,10 +13,10 @@
"llvm-target": "riscv32",
"max-atomic-width": 32,
"metadata": {
"description": "Bare RISC-V (RV32IMAC ISA)",
"host_tools": false,
"std": false,
"tier": 2
"description": null,
"host_tools": null,
"std": null,
"tier": null
},
"panic-strategy": "abort",
"relocation-model": "static",
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8 changes: 4 additions & 4 deletions support/targets/riscv32imac-sel4.json
Original file line number Diff line number Diff line change
Expand Up @@ -13,10 +13,10 @@
"llvm-target": "riscv32",
"max-atomic-width": 32,
"metadata": {
"description": "Bare RISC-V (RV32IMAC ISA)",
"host_tools": false,
"std": false,
"tier": 2
"description": null,
"host_tools": null,
"std": null,
"tier": null
},
"relocation-model": "static",
"target-pointer-width": "32"
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8 changes: 4 additions & 4 deletions support/targets/riscv32imafc-sel4-minimal.json
Original file line number Diff line number Diff line change
Expand Up @@ -14,10 +14,10 @@
"llvm-target": "riscv32",
"max-atomic-width": 32,
"metadata": {
"description": "Bare RISC-V (RV32IMAFC ISA)",
"host_tools": false,
"std": false,
"tier": 2
"description": null,
"host_tools": null,
"std": null,
"tier": null
},
"panic-strategy": "abort",
"relocation-model": "static",
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8 changes: 4 additions & 4 deletions support/targets/riscv32imafc-sel4.json
Original file line number Diff line number Diff line change
Expand Up @@ -14,10 +14,10 @@
"llvm-target": "riscv32",
"max-atomic-width": 32,
"metadata": {
"description": "Bare RISC-V (RV32IMAFC ISA)",
"host_tools": false,
"std": false,
"tier": 2
"description": null,
"host_tools": null,
"std": null,
"tier": null
},
"relocation-model": "static",
"target-pointer-width": "32"
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8 changes: 4 additions & 4 deletions support/targets/riscv64gc-sel4-microkit-minimal.json
Original file line number Diff line number Diff line change
Expand Up @@ -16,10 +16,10 @@
"llvm-target": "riscv64",
"max-atomic-width": 64,
"metadata": {
"description": "Bare RISC-V (RV64IMAFDC ISA)",
"host_tools": false,
"std": false,
"tier": 2
"description": null,
"host_tools": null,
"std": null,
"tier": null
},
"panic-strategy": "abort",
"relocation-model": "static",
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Original file line number Diff line number Diff line change
Expand Up @@ -16,10 +16,10 @@
"llvm-target": "riscv64",
"max-atomic-width": 64,
"metadata": {
"description": "Bare RISC-V (RV64IMAFDC ISA)",
"host_tools": false,
"std": false,
"tier": 2
"description": null,
"host_tools": null,
"std": null,
"tier": null
},
"panic-strategy": "abort",
"relocation-model": "static",
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8 changes: 4 additions & 4 deletions support/targets/riscv64gc-sel4-microkit-resettable.json
Original file line number Diff line number Diff line change
Expand Up @@ -16,10 +16,10 @@
"llvm-target": "riscv64",
"max-atomic-width": 64,
"metadata": {
"description": "Bare RISC-V (RV64IMAFDC ISA)",
"host_tools": false,
"std": false,
"tier": 2
"description": null,
"host_tools": null,
"std": null,
"tier": null
},
"relocation-model": "static",
"supported-sanitizers": [
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8 changes: 4 additions & 4 deletions support/targets/riscv64gc-sel4-microkit.json
Original file line number Diff line number Diff line change
Expand Up @@ -16,10 +16,10 @@
"llvm-target": "riscv64",
"max-atomic-width": 64,
"metadata": {
"description": "Bare RISC-V (RV64IMAFDC ISA)",
"host_tools": false,
"std": false,
"tier": 2
"description": null,
"host_tools": null,
"std": null,
"tier": null
},
"relocation-model": "static",
"supported-sanitizers": [
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8 changes: 4 additions & 4 deletions support/targets/riscv64gc-sel4-minimal.json
Original file line number Diff line number Diff line change
Expand Up @@ -15,10 +15,10 @@
"llvm-target": "riscv64",
"max-atomic-width": 64,
"metadata": {
"description": "Bare RISC-V (RV64IMAFDC ISA)",
"host_tools": false,
"std": false,
"tier": 2
"description": null,
"host_tools": null,
"std": null,
"tier": null
},
"panic-strategy": "abort",
"relocation-model": "static",
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8 changes: 4 additions & 4 deletions support/targets/riscv64gc-sel4.json
Original file line number Diff line number Diff line change
Expand Up @@ -15,10 +15,10 @@
"llvm-target": "riscv64",
"max-atomic-width": 64,
"metadata": {
"description": "Bare RISC-V (RV64IMAFDC ISA)",
"host_tools": false,
"std": false,
"tier": 2
"description": null,
"host_tools": null,
"std": null,
"tier": null
},
"relocation-model": "static",
"supported-sanitizers": [
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8 changes: 4 additions & 4 deletions support/targets/riscv64imac-sel4-microkit-minimal.json
Original file line number Diff line number Diff line change
Expand Up @@ -15,10 +15,10 @@
"llvm-target": "riscv64",
"max-atomic-width": 64,
"metadata": {
"description": "Bare RISC-V (RV64IMAC ISA)",
"host_tools": false,
"std": false,
"tier": 2
"description": null,
"host_tools": null,
"std": null,
"tier": null
},
"panic-strategy": "abort",
"relocation-model": "static",
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Original file line number Diff line number Diff line change
Expand Up @@ -15,10 +15,10 @@
"llvm-target": "riscv64",
"max-atomic-width": 64,
"metadata": {
"description": "Bare RISC-V (RV64IMAC ISA)",
"host_tools": false,
"std": false,
"tier": 2
"description": null,
"host_tools": null,
"std": null,
"tier": null
},
"panic-strategy": "abort",
"relocation-model": "static",
Expand Down
8 changes: 4 additions & 4 deletions support/targets/riscv64imac-sel4-microkit-resettable.json
Original file line number Diff line number Diff line change
Expand Up @@ -15,10 +15,10 @@
"llvm-target": "riscv64",
"max-atomic-width": 64,
"metadata": {
"description": "Bare RISC-V (RV64IMAC ISA)",
"host_tools": false,
"std": false,
"tier": 2
"description": null,
"host_tools": null,
"std": null,
"tier": null
},
"relocation-model": "static",
"supported-sanitizers": [
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8 changes: 4 additions & 4 deletions support/targets/riscv64imac-sel4-microkit.json
Original file line number Diff line number Diff line change
Expand Up @@ -15,10 +15,10 @@
"llvm-target": "riscv64",
"max-atomic-width": 64,
"metadata": {
"description": "Bare RISC-V (RV64IMAC ISA)",
"host_tools": false,
"std": false,
"tier": 2
"description": null,
"host_tools": null,
"std": null,
"tier": null
},
"relocation-model": "static",
"supported-sanitizers": [
Expand Down
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