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seed_riscv: get the thing actually working
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We were getting really weird behaviour before with the tracing stuff,
that was leading me to think code was being corrupted somehow. We seem to
have fixed that by stripping everything right back to basics and making
sure we're loading everything right, but I haven't convincingly found
the problem. Oh well - let's start adding stuff back and see what breaks.
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IsaacWoods committed Sep 6, 2022
1 parent f61ed38 commit 7b94d81
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Showing 7 changed files with 85 additions and 137 deletions.
Binary file modified bundled/ovmf/OVMF_VARS.fd
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39 changes: 1 addition & 38 deletions seed/Cargo.lock

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6 changes: 1 addition & 5 deletions seed/seed_riscv/Cargo.toml
Original file line number Diff line number Diff line change
Expand Up @@ -5,9 +5,5 @@ authors = ["Isaac Woods"]
edition = "2021"

[dependencies]
hal = { path = "../../lib/hal" }
hal_riscv = { path = "../../lib/hal_riscv" }
fdt = "0.1.3"
tracing = { git = "https://github.com/tokio-rs/tracing", default-features = false }
tracing-core = { git = "https://github.com/tokio-rs/tracing", default-features = false }
poplar_util = { path = "../../lib/poplar_util" }
log = "0.4.17"
50 changes: 27 additions & 23 deletions seed/seed_riscv/link.ld
Original file line number Diff line number Diff line change
@@ -1,46 +1,50 @@
OUTPUT_ARCH("riscv")
OUTPUT_FORMAT("elf64-littleriscv")
ENTRY(_start)

SECTIONS {
. = 0x80200000;
_kernel_start = .;

.text : {
*(.text.entry)
.text : ALIGN(16) {
*(.text.start)
*(.text .text.*)
. = ALIGN(4K);
}

.rodata : {
*(.rodata .rodata.*)
. = ALIGN(4K);
}

.data : {
*(.data .data.*)
.srodata : ALIGN(16) {
*(.srodata .srodata.*)
}

. = ALIGN(8);

.sdata : {
.sdata : ALIGN(16) {
*(.sdata .sdata.*)
. = ALIGN(4K);
}

.sbss : {
PROVIDE(__global_pointer$ = .);
PROVIDE(__bss_start = .);

.sbss : ALIGN(16) {
*(.sbss .sbss.*)
}

.bss : {
.bss : ALIGN(16) {
*(.bss .bss.*)
. = ALIGN(4K);

_stack_bottom = .;
. += 4K;
_stack_top = .;
PROVIDE(_stack_bottom = .);
. += 64K;
PROVIDE(_stack_top = .);
}

_kernel_end = .;
PROVIDE(__bss_end = .);

.data : ALIGN(16) {
*(.data .data.*)
}

.rodata : ALIGN(16) {
*(.rodata .rodata.*)
}

.eh_frame : ALIGN(16) {
*(.eh_frame)
}

/DISCARD/ : { *(.eh_frame_hdr .eh_frame) }
}
74 changes: 30 additions & 44 deletions seed/seed_riscv/src/logger.rs
Original file line number Diff line number Diff line change
@@ -1,60 +1,46 @@
use core::sync::atomic::{AtomicU64, Ordering};
use hal_riscv::hw::uart16550::Uart16550;
use poplar_util::InitGuard;
use tracing::{span, Collect, Event, Metadata};
use tracing_core::span::Current as CurrentSpan;
use core::{fmt, fmt::Write};
use log::{Level, LevelFilter, Metadata, Record};

static LOGGER: Logger = Logger::new();
pub struct Logger;

pub struct Logger {
next_id: AtomicU64,
serial_port: InitGuard<&'static mut Uart16550>,
}
static LOGGER: Logger = Logger;

impl Logger {
const fn new() -> Logger {
Logger { next_id: AtomicU64::new(0), serial_port: InitGuard::uninit() }
}

pub fn init() {
let serial_port = unsafe { &mut *(0x10000000 as *mut hal_riscv::hw::uart16550::Uart16550) };
LOGGER.serial_port.initialize(serial_port);
tracing::dispatch::set_global_default(tracing::dispatch::Dispatch::from_static(&LOGGER))
.expect("Failed to set default tracing dispatch");
log::set_logger(&LOGGER).map(|_| log::set_max_level(LevelFilter::Trace)).unwrap();
}
}

impl Collect for Logger {
fn current_span(&self) -> CurrentSpan {
todo!()
}

fn enabled(&self, _: &Metadata) -> bool {
true
}

fn enter(&self, span: &span::Id) {
todo!()
}

fn event(&self, event: &Event) {
todo!()
}
impl fmt::Write for Logger {
fn write_str(&mut self, s: &str) -> fmt::Result {
for byte in s.bytes() {
unsafe {
(0x1000_0000 as *mut u8).write_volatile(byte);
}
}

fn exit(&self, span: &span::Id) {
todo!()
Ok(())
}
}

fn new_span(&self, span: &span::Attributes) -> span::Id {
let mut id = self.next_id.fetch_add(1, Ordering::Acquire);
span::Id::from_u64(id)
impl log::Log for Logger {
fn enabled(&self, _metadata: &Metadata) -> bool {
true
}

fn record(&self, _span: &span::Id, _values: &span::Record) {
todo!()
fn log(&self, record: &Record) {
if self.enabled(record.metadata()) {
let color = match record.metadata().level() {
Level::Trace => "\x1b[36m",
Level::Debug => "\x1b[34m",
Level::Info => "\x1b[32m",
Level::Warn => "\x1b[33m",
Level::Error => "\x1b[31m",
};
writeln!(Logger, "[{}{:5}\x1b[0m] {}: {}", color, record.level(), record.target(), record.args())
.unwrap();
}
}

fn record_follows_from(&self, _span: &span::Id, _follows: &span::Id) {
todo!()
}
fn flush(&self) {}
}
50 changes: 24 additions & 26 deletions seed/seed_riscv/src/main.rs
Original file line number Diff line number Diff line change
Expand Up @@ -8,8 +8,8 @@
mod logger;

use fdt::Fdt;
use log::info;
use logger::Logger;
use tracing::info;

/*
* This is the entry-point jumped to from OpenSBI. It needs to be at the very start of the ELF, so we put it in its
Expand All @@ -19,70 +19,68 @@ use tracing::info;
*/
core::arch::global_asm!(
"
.section .text.entry
.section .text.start
.global _start
_start:
// Zero the BSS
la t0, __bss_start
la t1, __bss_end
bgeu t0, t1, .bss_zero_loop_end
.bss_zero_loop:
sd zero, (t0)
addi t0, t0, 8
bltu t0, t1, .bss_zero_loop
.bss_zero_loop_end:
la sp, _stack_top
mv fp, sp
j seed_main
jal seed_main
unimp
"
);

#[no_mangle]
pub fn seed_main(hart_id: usize, fdt: *const u8) -> ! {
pub fn seed_main(hart_id: u64, fdt: *const u8) -> ! {
assert!(fdt.is_aligned_to(8));

Logger::init();
info!("Hello, World!");
let uart = unsafe { &mut *(0x10000000 as *mut hal_riscv::hw::uart16550::Uart16550) };
use core::fmt::Write;
writeln!(uart, "Hello, World!").unwrap();
writeln!(uart, "HART ID: {}", hart_id).unwrap();
writeln!(uart, "FDT address: {:?}", fdt).unwrap();
info!("HART ID: {}", hart_id);
info!("FDT address: {:?}", fdt);
info!("Foo bar baz");

let fdt = unsafe { Fdt::from_ptr(fdt).expect("Failed to parse FDT") };
for region in fdt.memory().regions() {
writeln!(uart, "Memory region: {:?}", region).unwrap();
info!("Memory region: {:?}", region);
}
// for reservation in fdt.memory_reservations() {
// writeln!(uart, "Memory reservation: {:?}", reservation).unwrap();
// }
if let Some(reservations) = fdt.find_node("/reserved-memory") {
for child in reservations.children() {
writeln!(
uart,
"Memory reservation with name {}. Reg = {:?}",
child.name,
child.reg().unwrap().next().unwrap()
)
.unwrap();
info!("Memory reservation with name {}. Reg = {:?}", child.name, child.reg().unwrap().next().unwrap());
}
} else {
writeln!(uart, "No memory reservations :(").unwrap();
info!("No memory reservations :(");
}

writeln!(uart, "Looping :)").unwrap();
info!("Looping");
loop {}
}

#[panic_handler]
pub fn panic(info: &core::panic::PanicInfo) -> ! {
let uart = unsafe { &mut *(0x10000000 as *mut hal_riscv::hw::uart16550::Uart16550) };
use core::fmt::Write;

if let Some(message) = info.message() {
if let Some(location) = info.location() {
let _ = writeln!(
uart,
Logger,
"Panic message: {} ({} - {}:{})",
message,
location.file(),
location.line(),
location.column()
);
} else {
let _ = writeln!(uart, "Panic message: {} (no location info)", message);
let _ = writeln!(Logger, "Panic message: {} (no location info)", message);
}
}
loop {}
Expand Down
3 changes: 2 additions & 1 deletion tools/xtask/src/main.rs
Original file line number Diff line number Diff line change
Expand Up @@ -51,6 +51,7 @@ fn main() -> Result<()> {
}

TaskCmd::Clean(_) => {
clean(PathBuf::from("seed/"))?;
clean(PathBuf::from("kernel"))?;
clean(PathBuf::from("user"))?;
clean(PathBuf::from("lib/acpi"))?;
Expand Down Expand Up @@ -130,7 +131,7 @@ impl Dist {

let seed_riscv = RunCargo::new("seed_riscv", PathBuf::from("seed/seed_riscv/"))
.workspace(PathBuf::from("seed/"))
.target(Target::Triple("riscv64gc-unknown-none-elf".to_string()))
.target(Target::Triple("riscv64imac-unknown-none-elf".to_string()))
.release(self.release)
.features(self.kernel_features.clone())
.std_components(vec!["core".to_string(), "alloc".to_string()])
Expand Down

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