vxlan: fix port-range attribute endianness

Signed-off-by: Miguel Duarte Barroso <[email protected]>
rust-netlink · Aug 21, 2023 · ce406b2 · ce406b2
1 parent 927bdd7
commit ce406b2
Showing 1 changed file with 4 additions and 4 deletions.
diff --git a/src/rtnl/link/nlas/link_infos.rs b/src/rtnl/link/nlas/link_infos.rs
@@ -781,8 +781,8 @@ impl Nla for InfoVxlan {
             => buffer.copy_from_slice(value.as_slice()),
             Port(ref value) => BigEndian::write_u16(buffer, *value),
             PortRange(ref range) => {
-                NativeEndian::write_u16(buffer, range.0);
-                NativeEndian::write_u16(buffer, range.1)
+                BigEndian::write_u16(buffer, range.0);
+                BigEndian::write_u16(buffer, range.1)
             }
         }
     }
@@ -885,8 +885,8 @@ impl<'a, T: AsRef<[u8]> + ?Sized> Parseable<NlaBuffer<&'a T>> for InfoVxlan {
                 if payload.len() != 4 {
                     return Err(err.into());
                 }
-                let low = parse_u16(&payload[0..2]).context(err)?;
-                let high = parse_u16(&payload[2..]).context(err)?;
+                let low = parse_u16_be(&payload[0..2]).context(err)?;
+                let high = parse_u16_be(&payload[2..]).context(err)?;
                 PortRange((low, high))
             }
             IFLA_VXLAN_PORT => Port(