[WIP]

gen_intrinsics/src/main.rs

@@ -99,32 +99,44 @@ fn main() {
     let imports = obj.symbols().filter(|sym| sym.is_undefined()).collect::<Vec<_>>();
     assert!(imports.is_empty(), "{imports:?}");
 
-    for section in obj.sections() {
-        let section_name = section.name().unwrap();
-        if !section_name.starts_with(".text") {
-            continue;
-        }
+    for LlvmIntrinsicDef { abi: _, link_name, sig } in &visitor.llvm_intrinsics {
+        let section_name = format!(".text.__rust_cranelift_{}", link_name.replace('.', "__"));
+        let section = obj.section_by_name(&section_name).unwrap();
 
-        if section_name == ".text" {
-            assert_eq!(section.size(), 0);
-            continue;
-        }
-
-        let name = section_name.strip_prefix(".text.__rust_cranelift_").unwrap().replace("__", ".");
+        assert_ne!(section.size(), 0);
 
         // Sanity checks
-        assert!(section.relocations().next().is_none(), "function {name} has relocations");
+        assert!(section.relocations().next().is_none(), "function {link_name} has relocations");
         assert!(
             section.size() <= 0x14,
-            "function {name} is too big. it is {} bytes",
+            "function {link_name} is too big. it is {} bytes",
             section.size(),
         );
 
         let data = section.data().unwrap();
         let (code, ret) = data.split_at(data.len() - 4);
         assert_eq!(ret, [0xc0_u8, 0x03, 0x5f, 0xd6]); // arm64 ret instruction
-        println!("        \"{name}\" => {{");
-        println!("            {:x?}", code);
+
+        let args = sig
+            .inputs
+            .iter()
+            .map(|arg| match arg {
+                syn::FnArg::Typed(syn::PatType { pat, .. }) => match &**pat {
+                    syn::Pat::Ident(ident) => ident.ident.to_string(),
+                    _ => unreachable!("{pat:?}"),
+                },
+                _ => unreachable!(),
+            })
+            .collect::<Vec<_>>();
+
+        println!("        \"{link_name}\" => {{");
+        println!("            intrinsic_args!(fx, args => ({}); intrinsic);", args.join(", "));
+        println!(
+            "            call_asm(fx, \"{}\", &[{}], ret, &{:?});",
+            link_name.replace('.', "__"),
+            args.join(", "),
+            code
+        );
         println!("        }}");
     }
 }

src/intrinsics/llvm_aarch64.rs

@@ -1,8 +1,32 @@
 //! Emulate AArch64 LLVM intrinsics
 
+use cranelift_codegen::isa::CallConv;
+
 use crate::intrinsics::*;
 use crate::prelude::*;
 
+fn call_asm<'tcx>(
+    fx: &mut FunctionCx<'_, '_, 'tcx>,
+    name: &str,
+    args: &[CValue<'tcx>],
+    ret: CPlace<'tcx>,
+    code: &[u8],
+) {
+    let name = format!("__rust_cranelift_{name}");
+    let is_defined = fx.module.declarations().get_name(&name).is_none();
+
+    let sig = Signature { params: todo!(), returns: todo!(), call_conv: CallConv::SystemV };
+
+    let func = fx.module.declare_function(&name, Linkage::Local, &sig).unwrap();
+    if !is_defined {
+        todo!("define");
+    }
+
+    let func_ref = fx.module.declare_func_in_func(func, &mut fx.bcx.func);
+    let res = fx.bcx.ins().call(func_ref, &args.into_iter().map(|_| todo!()).collect::<Vec<_>>());
+    todo!("write result")
+}
+
 pub(crate) fn codegen_aarch64_llvm_intrinsic_call<'tcx>(
     fx: &mut FunctionCx<'_, '_, 'tcx>,
     intrinsic: &str,
@@ -309,6 +333,25 @@ pub(crate) fn codegen_aarch64_llvm_intrinsic_call<'tcx>(
             }
         }
 
+        // ==== begin autogenerated section ====
+        "llvm.trunc.v1f64" => {
+            intrinsic_args!(fx, args => (a); intrinsic);
+            call_asm(fx, "llvm__trunc__v1f64", &[a], ret, &[0, 192, 101, 30]);
+        }
+        "llvm.trunc.v2f32" => {
+            intrinsic_args!(fx, args => (a); intrinsic);
+            call_asm(fx, "llvm__trunc__v2f32", &[a], ret, &[0, 152, 161, 14]);
+        }
+        "llvm.trunc.v2f64" => {
+            intrinsic_args!(fx, args => (a); intrinsic);
+            call_asm(fx, "llvm__trunc__v2f64", &[a], ret, &[0, 152, 225, 78]);
+        }
+        "llvm.trunc.v4f32" => {
+            intrinsic_args!(fx, args => (a); intrinsic);
+            call_asm(fx, "llvm__trunc__v4f32", &[a], ret, &[0, 152, 161, 78]);
+        }
+        // ==== end autogenerated section
+
         /*
         _ if intrinsic.starts_with("llvm.aarch64.neon.sshl.v")
             || intrinsic.starts_with("llvm.aarch64.neon.sqshl.v")