Repo for AXIMasterSlaveStream Tutorial
./RunSimulation.py # should compile, build the model and run the testbench.
End result should look like:
TESTBENCH Passed! Data expected is equal to actual. expected = 0x00000000000000000000000000000000000000000000000000000000a7a7a7a7 actual = 0x00000000000000000000000000000000000000000000000000000000a7a7a7a7 Executing Axi4 End Of Simulation checks $finish called at time : 3885 ns : File "/home/rpease/AXIMasterSlaveStream/Verilog/tb/AXIMasterSlaveStreamIP_v1_0_tb.sv" Line 326