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Bug fix and ADC support for DE10 Nano
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robseb committed Jan 22, 2020
1 parent df63243 commit 5a66985
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89 changes: 89 additions & 0 deletions examples/python/adcDemo.py
Original file line number Diff line number Diff line change
@@ -0,0 +1,89 @@
#!/usr/bin/env python
# coding: utf-8

'''
@disc: ADC readout Sensor Test (Analog Devices LTC2308)
Fast way over the virtual memory
@date: 21.01.2020
@device: Intel Cyclone V
@author: Robin Sebastian
(https://github.com/robseb)
'''
import os
import time
import math
#
# This demo uses the python class "devmen" (https://github.com/kylemanna/pydevmem)
# be sure that this file is on the same directory
#
import devmem

# Demo duration
TEST_DURATIONS =30

# the Lightweight HPS-to-FPGA Bus base address offset
HPS_LW_ADRS_OFFSET = 0xFF200000

# LTC2308 Address offset
ADC_ADDRES_OFFSET = 0x40

# Register set of the LTC2308
ADC_CMD_REG_OFFSET = 0x0
ADC_DATA_REG_OFFSET = 0x4

#### Used ADC Channel
# Select here the ADC Channel for this Demo
ADC_CH = 1
##

### FIFO Convention Data Size for average calculation
FIFO_SIZE = 255 # MAX=1024

VALUE_OR_VOLTAGE_OUTPUT = 0 # 1: Raw Value output | 0: Volage

if __name__ == '__main__':
print("ADC readout Demo for LTC2308 ADC with Channel "+str(ADC_CH))

# open the memory Access to the Lightweight HPS-to-FPGA bridge
# (Base address, byte length to acceses, interface)
de = devmem.DevMem(HPS_LW_ADRS_OFFSET, ADC_ADDRES_OFFSET+0x8, "/dev/mem")

# Enter test loop
for var in range(TEST_DURATIONS):

# Set meassure number for ADC convert
de.write(ADC_ADDRES_OFFSET+ADC_DATA_REG_OFFSET,[FIFO_SIZE])
# Enable the convention with CH0
de.write(ADC_ADDRES_OFFSET+ADC_CMD_REG_OFFSET, [(ADC_CH <<1) | 0x00])
de.write(ADC_ADDRES_OFFSET+ADC_CMD_REG_OFFSET, [(ADC_CH <<1) | 0x01])
de.write(ADC_ADDRES_OFFSET+ADC_CMD_REG_OFFSET, [(ADC_CH <<1) | 0x00])

timeout = 300 #ms
# Wait untis convention is done or timeout
while (not(timeout == 0)):

if(de.read(ADC_ADDRES_OFFSET+ADC_CMD_REG_OFFSET,1)[0] & (1<<0)):
break

timeout = timeout -1
time.sleep(.001) # delay 1ms

# Avarage FIFO values
rawValue = 0
for i in range(FIFO_SIZE):
rawValue = rawValue+ (de.read(ADC_ADDRES_OFFSET+ADC_DATA_REG_OFFSET,1))[0]

value = rawValue / FIFO_SIZE

if VALUE_OR_VOLTAGE_OUTPUT:
value = round(value,2)
print("ADC AVG: "+str(value))
else:
# Convert ADC Value to Volage
volage = round(value/1000,2)
print("U AVG: "+str(volage)+"V")

time.sleep(.2) # 200ms delay

print('End of demo...')
108 changes: 108 additions & 0 deletions examples/python/adcTest.py
Original file line number Diff line number Diff line change
@@ -0,0 +1,108 @@
#!/usr/bin/env python
# coding: utf-8

'''
@disc: ADC readout Sensor Test (Analog Devices LTC2308)
Fast way over the virtual memory
@date: 21.01.2020
@device: Intel Cyclone V
@author: Robin Sebastian
(https://github.com/robseb)
'''
import os
import time
import math
import sys
#
# This demo uses the python class "devmen" (https://github.com/kylemanna/pydevmem)
# be sure that this file is on the same directory
#
import devmem

# Demo duration
TEST_DURATIONS =30

# the Lightweight HPS-to-FPGA Bus base address offset
HPS_LW_ADRS_OFFSET = 0xFF200000

# LTC2308 Address offset
ADC_ADDRES_OFFSET = 0x40

# Register set of the LTC2308
ADC_CMD_REG_OFFSET = 0x0
ADC_DATA_REG_OFFSET = 0x4

#### Used ADC Channel
# Select here the ADC Channel for this Demo
ADC_CH = 1
##

### FIFO Convention Data Size for average calculation
FIFO_SIZE = 255 # MAX=1024

VALUE_OR_VOLTAGE_OUTPUT = 0 # 1: Raw Value output | 0: Volage

if __name__ == '__main__':
print("ADC readout Demo for LTC2308 ADC with Channel "+str(ADC_CH))

# The ADC is only supported with rsYocto Version 1.031 or later
versionNo = 0
# The rsYocto Version Number is located here: "/usr/rsyocto/version.txt"
if os.path.isfile("/usr/rsyocto/version.txt"):
versionStr = ""
with open("/usr/rsyocto/version.txt", "r") as f:
versionStr = f.read()
# Convert String to int
try:
versionNo = float(versionStr)
except ValueError:
print("Warning: Failed to read rsYocto Version")

if not versionNo > 1.031:
print("Error: The ADC is only supported with rsYocto Version 1.031 or later ")
print(" This Version is: "+versionStr)
sys.exit()

# open the memory Access to the Lightweight HPS-to-FPGA bridge
# (Base address, byte length to acceses, interface)
de = devmem.DevMem(HPS_LW_ADRS_OFFSET, ADC_ADDRES_OFFSET+0x8, "/dev/mem")

# Enter test loop
for var in range(TEST_DURATIONS):

# Set meassure number for ADC convert
de.write(ADC_ADDRES_OFFSET+ADC_DATA_REG_OFFSET,[FIFO_SIZE])
# Enable the convention with CH0
de.write(ADC_ADDRES_OFFSET+ADC_CMD_REG_OFFSET, [(ADC_CH <<1) | 0x00])
de.write(ADC_ADDRES_OFFSET+ADC_CMD_REG_OFFSET, [(ADC_CH <<1) | 0x01])
de.write(ADC_ADDRES_OFFSET+ADC_CMD_REG_OFFSET, [(ADC_CH <<1) | 0x00])

timeout = 300 #ms
# Wait untis convention is done or timeout
while (not(timeout == 0)):

if(de.read(ADC_ADDRES_OFFSET+ADC_CMD_REG_OFFSET,1)[0] & (1<<0)):
break

timeout = timeout -1
time.sleep(.001) # delay 1ms

# Avarage FIFO values
rawValue = 0
for i in range(FIFO_SIZE):
rawValue = rawValue+ (de.read(ADC_ADDRES_OFFSET+ADC_DATA_REG_OFFSET,1))[0]

value = rawValue / FIFO_SIZE

if VALUE_OR_VOLTAGE_OUTPUT:
value = round(value,2)
print("ADC AVG: "+str(value))
else:
# Convert ADC Value to Volage
volage = round(value/1000,2)
print("U AVG: "+str(volage)+"V")

time.sleep(.2) # 200ms delay

print('End of demo...')
Binary file modified fpga/DE10NANOrsyocto.qar
Binary file not shown.
62 changes: 33 additions & 29 deletions fpga/DE10NANOrsyocto.v
Original file line number Diff line number Diff line change
Expand Up @@ -19,7 +19,7 @@

`define USE_HPS
`define USE_ADUINO

`define USE_ADC
// `define USE_HDMI
// `define USE_GPIO0
// `define USE_GPIO1
Expand Down Expand Up @@ -88,10 +88,6 @@ module DE10NANOrsyocto(
output [3:0] HPS_ENET_TX_DATA,
output HPS_ENET_TX_EN,

//inout HPS_GSENSOR_INT,
//inout HPS_I2C0_SCLK,
//inout HPS_I2C0_SDAT,

inout HPS_I2C1_SCLK,
inout HPS_I2C1_SDAT,

Expand Down Expand Up @@ -163,29 +159,29 @@ wire can0_rx, can0_tx;
base_hps u0 (

/////////////////////////////////////////////// CLOCKS ////////////////////////////////////////////////
.clk_clk (CLOCK_50),
.clk_clk ( FPGA_CLK1_50 ),

///////////////////////////////////////////////////////////////////////////////////////////////////////
///////////////////////////////////////// HPS ///////////////////////////////////////////////////
///////////////////////////////////////////////////////////////////////////////////////////////////////

///////////////////////////////////// Onboard DDR3 1GB Memmory //////////////////////////////////////
.hps_0_ddr_mem_a ( HPS_DDR3_ADDR),
.hps_0_ddr_mem_ba ( HPS_DDR3_BA),
.hps_0_ddr_mem_ck ( HPS_DDR3_CK_P),
.hps_0_ddr_mem_ck_n ( HPS_DDR3_CK_N),
.hps_0_ddr_mem_cke ( HPS_DDR3_CKE),
.hps_0_ddr_mem_cs_n ( HPS_DDR3_CS_N),
.hps_0_ddr_mem_ras_n ( HPS_DDR3_RAS_N),
.hps_0_ddr_mem_cas_n ( HPS_DDR3_CAS_N),
.hps_0_ddr_mem_we_n ( HPS_DDR3_WE_N),
.hps_0_ddr_mem_reset_n ( HPS_DDR3_RESET_N),
.hps_0_ddr_mem_dq ( HPS_DDR3_DQ),
.hps_0_ddr_mem_dqs ( HPS_DDR3_DQS_P),
.hps_0_ddr_mem_dqs_n ( HPS_DDR3_DQS_N),
.hps_0_ddr_mem_odt ( HPS_DDR3_ODT),
.hps_0_ddr_mem_dm ( HPS_DDR3_DM),
.hps_0_ddr_oct_rzqin ( HPS_DDR3_RZQ),
.hps_0_ddr_mem_a ( HPS_DDR3_ADDR),
.hps_0_ddr_mem_ba ( HPS_DDR3_BA),
.hps_0_ddr_mem_ck ( HPS_DDR3_CK_P),
.hps_0_ddr_mem_ck_n ( HPS_DDR3_CK_N),
.hps_0_ddr_mem_cke ( HPS_DDR3_CKE),
.hps_0_ddr_mem_cs_n ( HPS_DDR3_CS_N),
.hps_0_ddr_mem_ras_n ( HPS_DDR3_RAS_N),
.hps_0_ddr_mem_cas_n ( HPS_DDR3_CAS_N),
.hps_0_ddr_mem_we_n ( HPS_DDR3_WE_N),
.hps_0_ddr_mem_reset_n ( HPS_DDR3_RESET_N),
.hps_0_ddr_mem_dq ( HPS_DDR3_DQ),
.hps_0_ddr_mem_dqs ( HPS_DDR3_DQS_P),
.hps_0_ddr_mem_dqs_n ( HPS_DDR3_DQS_N),
.hps_0_ddr_mem_odt ( HPS_DDR3_ODT),
.hps_0_ddr_mem_dm ( HPS_DDR3_DM),
.hps_0_ddr_oct_rzqin ( HPS_DDR3_RZQ),

///////////////////////////////////////// HPS Ethernet 1 ////////////////////////////////////////////
.hps_0_io_hps_io_emac1_inst_TX_CLK ( HPS_ENET_GTX_CLK),
Expand Down Expand Up @@ -275,11 +271,19 @@ base_hps u0 (
.hps_0_spim0_ss_3_n (),



///////////////////////////////////////////////////////////////////////////////////////////////////////
////////////////////////////////// On Board Compunents ////////////////////////////////////////
///////////////////////////////////////////////////////////////////////////////////////////////////////


/////////////////////////////////////////// Analog Devices LTC2308 ////////////////////////////////

.adc_ltc2308_conduit_end_CONVST (ADC_CONVST),
.adc_ltc2308_conduit_end_SCK (ADC_SCK),
.adc_ltc2308_conduit_end_SDI (ADC_SDI),
.adc_ltc2308_conduit_end_SDO (ADC_SDO),


/////////////////////////////////////////// HPS LED & KEY ///////////////////////////////////////////
.hps_0_io_hps_io_gpio_inst_GPIO53 ( HPS_LED),
.hps_0_io_hps_io_gpio_inst_GPIO54 ( HPS_KEY),
Expand All @@ -289,15 +293,16 @@ base_hps u0 (
.hps_0_io_hps_io_i2c0_inst_SCL (HPS_I2C1_SCLK),

/////////////////////////////////// onboard LEDs, Switches and Keys ///////////////////////////////////
.led_pio_external_connection_export (LEDR),
.led_pio_external_connection_export (LED),
.pb_pio_external_connection_export (KEY),
.sw_pio_external_connection_export (SW),



////////////////////////////////// HPS -> FPGA GPIO ///////////////////////////////////
.hps_0_h2f_gp_gp_in (32'hACDCACDC),
.hps_0_h2f_gp_gp_out ()
// 32-Bit direct access registry between HPS and FPGA
.hps_0_h2f_gp_gp_in (32'hACDCACDC), // FPGA to HPS -->
.hps_0_h2f_gp_gp_out () // HPS to FPGA <--
);


Expand Down Expand Up @@ -329,7 +334,7 @@ base_hps u0 (
///////////////////////////////////////////


//////////////////////////////////////// IO Buffer SPI 0 /////////////////////////////////////////////
////////////////////////////////////////// IO Buffer SPI 0 /////////////////////////////////////////////
// SPI0 -> CS
ALT_IOBUF spi0_ss_iobuf (.i(spi0_ss_0_n), .oe(1'b1), .o(), .io(ARDUINO_IO[10]));
// SPI0 -> MOSI
Expand All @@ -339,7 +344,7 @@ base_hps u0 (
// SPI0 -> CLK
ALT_IOBUF spi0_clk_iobuf (.i(spi0_clk), .oe(1'b1), .o(), .io(ARDUINO_IO[13]));

////////////////////////////////////////// IO Buffer I2C 1 and 3 /////////////////////////////////////
////////////////////////////////////////// IO Buffer I2C 1 and 3 //////////////////////////////////////
// I2C1 -> SCL
ALT_IOBUF i2c1_scl_iobuf (.i(1'b0),.oe(scl1_o_e),.o(scl1_o),.io(ARDUINO_IO[15]));
// I2C1 -> SDA
Expand All @@ -363,7 +368,6 @@ base_hps u0 (
ALT_IOBUF can0_tx_iobuf (.i(can0_tx), .oe(1'b1), .o(), .io(ARDUINO_IO[8]));



endmodule


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