fix table title; update submodule; blank lines between blocks

Signed-off-by: Kevin Broch <[email protected]>
riscvarchive · Jan 24, 2024 · eceea76 · eceea76
1 parent eda0269
commit eceea76
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diff --git a/body.adoc b/body.adoc
@@ -20,9 +20,7 @@ with counter _i_ can be read or written via sireg*, while siselect holds
 0x40+__i__. The counter state accessible via alias CSRs is shown in
 Table 1 below.
 
-[.text-center]
-*Table 1.* Indirect HPM State Mappings
-
+.Indirect HPM State Mappings
 [width="100%",cols="21%,20%,21%,18%,20%",options="header",]
 |===
 |*siselect value* |*sireg* |*sireg4* |*sireg2* |*sireg5*
@@ -144,6 +142,7 @@ optional whether the LCOFI bit (bit 13) in each of mideleg and hideleg,
 which allows all LCOFIs to be delegated to S-mode and VS-mode,
 respectively, is implemented and writable._
 ====
+
 [NOTE]
 ====
 __In a production “Rich OS” environment, it is expected that M-mode

diff --git a/docs-resources b/docs-resources
diff --git a/header.adoc b/header.adoc
@@ -57,6 +57,7 @@ Copyright 2023-2024 by RISC-V International.
 include::contributors.adoc[]
 
 include::intro.adoc[]
+
 include::body.adoc[]
 
 // The index must precede the bibliography