Support Q-extension #99

kito-cheng · 2017-09-26T15:25:31Z

Not testing with spike yet, but able to build rv64gq toolchain.

Loads on RISC-V are sign-extending by default, but we weren't telling GCC this in our PIC load patterns. This corrects the problem, and adds a zero-extending pattern as well. gcc/ChangeLog 2017-05-09 Palmer Dabbelt <[email protected]> * config/riscv/riscv.md (ZERO_EXTEND_LOAD): Define. * config/riscv/pic.md (local_pic_load): Rename to local_pic_load_s, mark as a sign-extending load. (local_pic_load_u): Define.

GCC may generate non-legitimate address due to we allow some load/store with non-legitimate address in pic.md. 2017-05-12 Kito Cheng <[email protected]> * config/riscv/riscv.c (riscv_legitimize_move): Handle non-legitimate address.

…mtune 2017-05-18 Andrew Waterman <[email protected]> * config/riscv/riscv.c (riscv_option_override): Conditionally set TARGET_STRICT_ALIGN based upon -mtune argument.

This documentation is patterned off the aarch64 -mcmodel documentation. gcc/ChangeLog: 2017-07-27 Palmer Dabbelt <[email protected]> * doc/invoke.texi (RISC-V Options): Explicitly name the medlow and medany code models, and describe what they do.

This changes makes GCC asm output use instruction names that are consistent with the RISC-V ISA manual. - Add 'i' letter to riscv_print_operand that prints an i character if the operand is not a register. - Update riscv.md to add %i2 to instructions with register register and register immediate variants.

https://gcc.gnu.org/ml/gcc/2017-08/msg00202.html We should make sure this doesn't regress on the test suite before sending upstream.

See https://github.com/riscv/riscv-elf-psabi-doc/blob/master/riscv-elf.md

This reverts commit 18b6db6.

This supports reducing the stack alignment to 8 bytes for RV32I.

kito-cheng · 2017-09-26T15:25:51Z

DO NOT MERGE until testing done.

kito-cheng · 2017-09-28T04:51:36Z

@aswaterman btw, I was implemented Q extension for RV32 too, however binutils forbid RV32*Q now, should I support that? I've removed those part in this PR.

aswaterman · 2017-09-28T05:02:19Z

I think for now we should forbid RV32Q everywhere. If the RISC-V Foundation decides RV32Q should be supported in the future, we can enable it. But going the other direction is much harder :)

kito-cheng · 2017-09-28T05:09:42Z

OK, so I just discard those code :P

aswaterman · 2017-09-28T05:17:35Z

Yeah, but maybe don't delete the branch, so we can revive it later if we want.

kito-cheng · 2017-09-28T05:35:55Z

Hmm, hold the code gen part but forbid in -march (forbid all rv32q), and -mabi (forbid ilp32q) ?

aswaterman · 2017-09-28T06:02:50Z

Yeah, that sounds like a good idea to me. @palmer-dabbelt OK?

kito-cheng · 2017-10-12T03:11:45Z

Current test result:

                                    |   rv64imafd   |      rv64gq   | 
gcc       # of expected failures    |         154   |         154   | 
          # of expected passes      |       89050   |       88872   | 
          # of unexpected failures  |           6   |         184   | 
          # of unexpected successes |           4   |           4   | 
          # of unresolved testcases |           1   |           1   | 
          # of unsupported tests    |        2198   |        2198   | 
g++       # of expected failures    |         318   |         318   | 
          # of expected passes      |       94489   |       94406   | 
          # of unexpected failures  |           9   |          92   | 
          # of unexpected successes |           0   |           0   | 
          # of unresolved testcases |           0   |           0   | 
          # of unsupported tests    |        4670   |        4670   |

Simulator: spike
Note: rv64imafd as golden

kito-cheng · 2017-10-12T03:13:43Z

Fail cases:

gcc

gcc.c-torture/execute/conversion.c
gcc.c-torture/execute/pr56982.c
gcc.c-torture/execute/ieee/copysign1.c
gcc.c-torture/execute/ieee/copysign2.c
gcc.c-torture/execute/ieee/fp-cmp-4l.c
gcc.dg/compat/scalar-by-value-3
gcc.dg/compat/struct-by-value-18
gcc.dg/compat/struct-by-value-18a
c-c++-common/patchable_function_entry-decl.c
c-c++-common/patchable_function_entry-default.c
c-c++-common/patchable_function_entry-definition.c
gcc.dg/float-exact-1.c
gcc.dg/pr21643.c
gcc.dg/pr28796-2.c
gcc.dg/tls/pr78796.c
c-c++-common/torture/complex-sign-add.c
c-c++-common/torture/complex-sign-mixed-add.c
c-c++-common/torture/complex-sign-mixed-div.c
c-c++-common/torture/complex-sign-mixed-mul.c
c-c++-common/torture/complex-sign-mixed-sub.c
c-c++-common/torture/complex-sign-mul-minus-one.c
c-c++-common/torture/complex-sign-mul-one.c
c-c++-common/torture/complex-sign-mul.c
c-c++-common/torture/complex-sign-sub.c
gcc.dg/torture/builtin-complex-1.c
gcc.dg/torture/float128-floath.c
gcc.dg/torture/float128-tg-3.c
gcc.dg/torture/float64x-floath.c
gcc.dg/torture/float64x-tg-3.c
gcc.dg/torture/fp-int-convert-float128-ieee-timode.c
gcc.dg/torture/fp-int-convert-float128-ieee.c
gcc.dg/torture/fp-int-convert-float64x-timode.c
gcc.dg/torture/fp-int-convert-float64x.c
gcc.dg/torture/fp-int-convert-long-double.c
gcc.dg/torture/fp-int-convert-timode.c
gcc.dg/torture/pr48542.c
gcc.dg/torture/type-generic-1.c
gcc.dg/tree-ssa/builtin-sprintf.c
gcc.dg/tree-ssa/phi-opt-11.c

g++

c-c++-common/torture/complex-sign-add.c
c-c++-common/torture/complex-sign-mixed-add.c
c-c++-common/torture/complex-sign-mixed-div.c
c-c++-common/torture/complex-sign-mixed-mul.c
c-c++-common/torture/complex-sign-mixed-sub.c
c-c++-common/torture/complex-sign-mul-minus-one.c
c-c++-common/torture/complex-sign-mul-one.c
c-c++-common/torture/complex-sign-mul.c
c-c++-common/torture/complex-sign-sub.c
g++.dg/torture/type-generic-1.C
g++.old-deja/g++.abi/cxa_vec.C

kito-cheng · 2017-10-13T10:41:31Z

Current status:

                                    |   rv64imafd   |      rv64gq       | 
gcc       # of expected failures    |         154   |         154       | 
          # of expected passes      |       89050   |       89035       | 
          # of unexpected failures  |           6   |          21 (-163)| 
          # of unexpected successes |           4   |           4       | 
          # of unresolved testcases |           1   |           1       | 
          # of unsupported tests    |        2198   |        2198       | 
g++       # of expected failures    |         318   |         318       | 
          # of expected passes      |       94489   |       94484       | 
          # of unexpected failures  |           9   |          14 (-78) | 
          # of unexpected successes |           0   |           0       | 
          # of unresolved testcases |           0   |           0       | 
          # of unsupported tests    |        4670   |        4670       |

palmer-dabbelt and others added 15 commits July 31, 2017 16:37

RISC-V: If -m[no-]strict-align is not passed, assume its value from -…

a3b04ab

…mtune 2017-05-18 Andrew Waterman <[email protected]> * config/riscv/riscv.c (riscv_option_override): Conditionally set TARGET_STRICT_ALIGN based upon -mtune argument.

Set SLOW_BYTE_ACCESS=1

06ab509

https://gcc.gnu.org/ml/gcc/2017-08/msg00202.html We should make sure this doesn't regress on the test suite before sending upstream.

Implement __umulsidi3, umul_ppmm and __muluw3 for RISC-V

843c725

Replace multi3.S with C version implementation

70f5bdf

Support RV32E

a989611

Remove redundant sign-extension uint32_t >> constant

5f200df

For RV32I ABIs, stack alignment should only be 64 bits

18b6db6

See https://github.com/riscv/riscv-elf-psabi-doc/blob/master/riscv-elf.md

Emit small read-only data into .srodata section

a29f49e

Revert "For RV32I ABIs, stack alignment should only be 64 bits"

3d5c8c0

This reverts commit 18b6db6.

Support -mpreferred-stack-boundary flag

ed96839

This supports reducing the stack alignment to 8 bytes for RV32I.

Support Q-extension

dd2c61f

kito-cheng mentioned this pull request Sep 26, 2017

Implement Q extension riscv-software-src/riscv-isa-sim#129

Merged

palmer-dabbelt force-pushed the riscv-next branch 3 times, most recently from da145f4 to d45838f Compare October 25, 2017 23:18

palmer-dabbelt force-pushed the riscv-next branch from a0abddc to ac43954 Compare October 31, 2017 18:32

palmer-dabbelt force-pushed the riscv-next branch 12 times, most recently from 61a42d9 to d2cc398 Compare November 8, 2017 23:56

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Support Q-extension #99

Support Q-extension #99

kito-cheng commented Sep 26, 2017

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kito-cheng commented Oct 13, 2017

Support Q-extension #99

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