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rename v* constraint to C*
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@linsinan1995 @sinan-lin
linsinan1995 authored and sinan-lin committed May 18, 2021

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Showing 3 changed files with 78 additions and 78 deletions.
16 changes: 8 additions & 8 deletions gcc/config/riscv/constraints.md
View file
Original file line number Diff line number Diff line change
@@ -107,32 +107,32 @@
(and (match_code "const_int")
(match_test "ival < (1 << 6) && ival >= 0")))

(define_constraint "v00"
(define_constraint "C00"
"Constant value 1"
(and (match_code "const_int")
(match_test "ival == 0")))

(define_constraint "v01"
(define_constraint "C01"
"Constant value 1"
(and (match_code "const_int")
(match_test "ival == 1")))

(define_constraint "v02"
(define_constraint "C02"
"Constant value 2"
(and (match_code "const_int")
(match_test "ival == 2")))

(define_constraint "v03"
(define_constraint "C03"
"Constant value 3"
(and (match_code "const_int")
(match_test "ival == 3")))

(define_constraint "v04"
(define_constraint "C04"
"Constant value 4"
(and (match_code "const_int")
(match_test "ival == 4")))

(define_constraint "v08"
(define_constraint "C08"
"Constant value 8"
(and (match_code "const_int")
(match_test "ival == 8")))
@@ -142,12 +142,12 @@
(and (match_code "const_int")
(match_test "(unsigned) exact_log2 (ival) <= 7")))

(define_constraint "v15"
(define_constraint "C15"
"Constant value 15"
(and (match_code "const_int")
(match_test "ival == 15")))

(define_constraint "v16"
(define_constraint "C16"
"Constant value 16"
(and (match_code "const_int")
(match_test "ival == 16")))
24 changes: 12 additions & 12 deletions gcc/config/riscv/predicates.md
View file
Original file line number Diff line number Diff line change
@@ -255,10 +255,10 @@

(define_predicate "imm_1_2_4_8_operand"
(and (match_operand 0 "const_int_operand")
(ior (ior (match_test "satisfies_constraint_v01 (op)")
(match_test "satisfies_constraint_v02 (op)"))
(ior (match_test "satisfies_constraint_v04 (op)")
(match_test "satisfies_constraint_v08 (op)")))))
(ior (ior (match_test "satisfies_constraint_C01 (op)")
(match_test "satisfies_constraint_C02 (op)"))
(ior (match_test "satisfies_constraint_C04 (op)")
(match_test "satisfies_constraint_C08 (op)")))))

(define_predicate "pwr_7_operand"
(and (match_code "const_int")
@@ -267,20 +267,20 @@

(define_predicate "imm_0_1_operand"
(and (match_operand 0 "const_int_operand")
(ior (match_test "satisfies_constraint_v00 (op)")
(match_test "satisfies_constraint_v01 (op)"))))
(ior (match_test "satisfies_constraint_C00 (op)")
(match_test "satisfies_constraint_C01 (op)"))))

(define_predicate "imm_1_2_operand"
(and (match_operand 0 "const_int_operand")
(ior (match_test "satisfies_constraint_v01 (op)")
(match_test "satisfies_constraint_v02 (op)"))))
(ior (match_test "satisfies_constraint_C01 (op)")
(match_test "satisfies_constraint_C02 (op)"))))

(define_predicate "imm_2_3_operand"
(and (match_operand 0 "const_int_operand")
(ior (match_test "satisfies_constraint_v02 (op)")
(match_test "satisfies_constraint_v03 (op)"))))
(ior (match_test "satisfies_constraint_C02 (op)")
(match_test "satisfies_constraint_C03 (op)"))))

(define_predicate "imm_15_16_operand"
(and (match_operand 0 "const_int_operand")
(ior (match_test "satisfies_constraint_v15 (op)")
(match_test "satisfies_constraint_v16 (op)"))))
(ior (match_test "satisfies_constraint_C15 (op)")
(match_test "satisfies_constraint_C16 (op)"))))
116 changes: 58 additions & 58 deletions gcc/config/riscv/rvp.md
View file
Original file line number Diff line number Diff line change
@@ -1222,7 +1222,7 @@
(vec_duplicate:V4QI
(match_operand:QI 1 "register_operand" " r, r, r, r"))
(match_operand:V4QI 2 "register_operand" " 0, 0, 0, 0")
(match_operand:SI 3 "imm_1_2_4_8_operand" " v01, v02, v04, v08")))]
(match_operand:SI 3 "imm_1_2_4_8_operand" " C01, C02, C04, C08")))]
"TARGET_ZPN && !TARGET_64BIT"
"@
insb\t%0, %1, 0
@@ -1345,11 +1345,11 @@
(sign_extend:SI
(vec_select:HI
(match_operand:V2HI 1 "register_operand" " r, r, r, r")
(parallel [(match_operand:SI 3 "imm_0_1_operand" " v00, v00, v01, v01")])))
(parallel [(match_operand:SI 3 "imm_0_1_operand" " C00, C00, C01, C01")])))
(sign_extend:SI
(vec_select:HI
(match_operand:V2HI 2 "register_operand" " r, r, r, r")
(parallel [(match_operand:SI 4 "imm_0_1_operand" " v00, v01, v01, v00")]))))
(parallel [(match_operand:SI 4 "imm_0_1_operand" " C00, C01, C01, C00")]))))
(const_int 1))
(match_operand:SI 5 "register_operand" " 0, 0, 0, 0")))]
"TARGET_ZPN"
@@ -1410,11 +1410,11 @@
(sign_extend:SI
(vec_select:HI
(match_operand:V4HI 1 "register_operand" " r, r, r, r")
(parallel [(match_operand:SI 3 "imm_0_1_operand" " v00, v00, v01, v01")])))
(parallel [(match_operand:SI 3 "imm_0_1_operand" " C00, C00, C01, C01")])))
(sign_extend:SI
(vec_select:HI
(match_operand:V4HI 2 "register_operand" " r, r, r, r")
(parallel [(match_operand:SI 4 "imm_0_1_operand" " v00, v01, v01, v00")]))))
(parallel [(match_operand:SI 4 "imm_0_1_operand" " C00, C01, C01, C00")]))))
(const_int 1))
(match_operand:SI 5 "register_operand" " 0, 0, 0, 0")))]
"TARGET_ZPN && TARGET_64BIT"
@@ -1474,11 +1474,11 @@
(sign_extend:SI
(vec_select:HI
(match_operand:V2HI 1 "register_operand" " r, r, r, r")
(parallel [(match_operand:SI 3 "imm_0_1_operand" " v00, v00, v01, v01")])))
(parallel [(match_operand:SI 3 "imm_0_1_operand" " C00, C00, C01, C01")])))
(sign_extend:SI
(vec_select:HI
(match_operand:V2HI 2 "register_operand" " r, r, r, r")
(parallel [(match_operand:SI 4 "imm_0_1_operand" " v00, v01, v01, v00")]))))
(parallel [(match_operand:SI 4 "imm_0_1_operand" " C00, C01, C01, C00")]))))
(const_int 1))
(match_operand:SI 5 "register_operand" " 0, 0, 0, 0")))]
"TARGET_ZPN"
@@ -1598,11 +1598,11 @@
(sign_extend:SI
(vec_select:HI
(match_operand:V2HI 1 "register_operand" " r, r, r, r")
(parallel [(match_operand:SI 3 "imm_0_1_operand" " v00, v00, v01, v01")])))
(parallel [(match_operand:SI 3 "imm_0_1_operand" " C00, C00, C01, C01")])))
(sign_extend:SI
(vec_select:HI
(match_operand:V2HI 2 "register_operand" " r, r, r, r")
(parallel [(match_operand:SI 4 "imm_0_1_operand" " v00, v01, v01, v00")]))))
(parallel [(match_operand:SI 4 "imm_0_1_operand" " C00, C01, C01, C00")]))))
(match_operand:SI 5 "register_operand" " 0, 0, 0, 0")))]
"TARGET_ZPN && !TARGET_64BIT"
{
@@ -1664,13 +1664,13 @@
(sign_extend:V2SI
(vec_select:V2HI
(match_operand:V4HI 1 "register_operand" " r, r, r, r")
(parallel [(match_operand:SI 3 "imm_0_1_operand" " v00, v00, v01, v01")
(match_operand:SI 4 "imm_2_3_operand" " v02, v02, v03, v03")])))
(parallel [(match_operand:SI 3 "imm_0_1_operand" " C00, C00, C01, C01")
(match_operand:SI 4 "imm_2_3_operand" " C02, C02, C03, C03")])))
(sign_extend:V2SI
(vec_select:V2HI
(match_operand:V4HI 2 "register_operand" " r, r, r, r")
(parallel [(match_operand:SI 5 "imm_0_1_operand" " v00, v01, v01, v00")
(match_operand:SI 6 "imm_2_3_operand" " v02, v03, v03, v02")]))))
(parallel [(match_operand:SI 5 "imm_0_1_operand" " C00, C01, C01, C00")
(match_operand:SI 6 "imm_2_3_operand" " C02, C03, C03, C02")]))))
(match_operand:V2SI 7 "register_operand" " 0, 0, 0, 0")))]
"TARGET_ZPN && TARGET_64BIT"
"@
@@ -2144,8 +2144,8 @@
(sign_extend:DI
(vec_select:HI
(match_operand:V2HI 2 "register_operand" " r, r, r, r")
(parallel [(match_operand:SI 3 "imm_0_1_operand" " v00, v01, v00, v01")]))))
(match_operand:SI 5 "imm_15_16_operand" " v16, v16, v15, v15" )))))]
(parallel [(match_operand:SI 3 "imm_0_1_operand" " C00, C01, C00, C01")]))))
(match_operand:SI 5 "imm_15_16_operand" " C16, C16, C15, C15" )))))]
"TARGET_ZPN && !TARGET_64BIT"
"@
kmmawb\t%0, %1, %2
@@ -2218,9 +2218,9 @@
(sign_extend:DI
(vec_select:HI
(match_operand:V2HI 2 "register_operand" " r, r, r, r")
(parallel [(match_operand:SI 3 "imm_0_1_operand" " v00, v01, v00, v01")]))))]
(parallel [(match_operand:SI 3 "imm_0_1_operand" " C00, C01, C00, C01")]))))]
UNSPEC_ROUND)
(match_operand:SI 5 "imm_15_16_operand" " v16, v16, v15, v15")))))]
(match_operand:SI 5 "imm_15_16_operand" " C16, C16, C15, C15")))))]
"TARGET_ZPN && !TARGET_64BIT"
"@
kmmawb.u\t%0, %1, %2
@@ -2296,8 +2296,8 @@
(sign_extend:DI
(vec_select:HI
(match_operand:V4HI 2 "register_operand" " r, r, r, r")
(parallel [(match_operand:SI 3 "imm_0_1_operand" "v00, v01, v00, v01")]))))
(match_operand:SI 6 "imm_15_16_operand" "v16, v16, v15, v15")))
(parallel [(match_operand:SI 3 "imm_0_1_operand" "C00, C01, C00, C01")]))))
(match_operand:SI 6 "imm_15_16_operand" "C16, C16, C15, C15")))
(truncate:SI
(lshiftrt:DI
(mult:DI
@@ -2308,7 +2308,7 @@
(sign_extend:DI
(vec_select:HI
(match_dup 2)
(parallel [(match_operand:SI 4 "imm_2_3_operand" "v02, v03, v02, v03")]))))
(parallel [(match_operand:SI 4 "imm_2_3_operand" "C02, C03, C02, C03")]))))
(match_dup 6))))))]
"TARGET_ZPN && TARGET_64BIT"
"@
@@ -2390,7 +2390,7 @@
(sign_extend:DI
(vec_select:HI
(match_operand:V4HI 2 "register_operand" " r, r, r, r")
(parallel [(match_operand:SI 3 "imm_0_1_operand" "v00, v01, v00, v01")]))))]
(parallel [(match_operand:SI 3 "imm_0_1_operand" "C00, C01, C00, C01")]))))]
UNSPEC_ROUND)
(const_int 16)))
(truncate:SI
@@ -2404,9 +2404,9 @@
(sign_extend:DI
(vec_select:HI
(match_dup 2)
(parallel [(match_operand:SI 4 "imm_2_3_operand" "v02, v03, v02, v03")]))))]
(parallel [(match_operand:SI 4 "imm_2_3_operand" "C02, C03, C02, C03")]))))]
UNSPEC_ROUND)
(match_operand:SI 6 "imm_15_16_operand" "v16, v16, v15, v15"))))))]
(match_operand:SI 6 "imm_15_16_operand" "C16, C16, C15, C15"))))))]
"TARGET_ZPN && TARGET_64BIT"
"@
kmmawb.u\t%0, %1, %2
@@ -2537,7 +2537,7 @@
(sign_extend:DI
(vec_select:HI
(match_operand:V2HI 2 "register_operand" " r, r")
(parallel [(match_operand:SI 3 "imm_0_1_operand" " v00, v01")]))))]
(parallel [(match_operand:SI 3 "imm_0_1_operand" " C00, C01")]))))]
UNSPEC_KMMWU)
(const_int 15))))]
"TARGET_ZPN && !TARGET_64BIT"
@@ -2584,7 +2584,7 @@
(sign_extend:DI
(vec_select:HI
(match_operand:V4HI 2 "register_operand" " r, r")
(parallel [(match_operand:SI 3 "imm_0_1_operand" "v00, v01")]))))]
(parallel [(match_operand:SI 3 "imm_0_1_operand" "C00, C01")]))))]
UNSPEC_KMMWU)
(const_int 15)))
(truncate:SI
@@ -2598,7 +2598,7 @@
(sign_extend:DI
(vec_select:HI
(match_dup 2)
(parallel [(match_operand:SI 4 "imm_2_3_operand" "v02, v03")]))))]
(parallel [(match_operand:SI 4 "imm_2_3_operand" "C02, C03")]))))]
UNSPEC_KMMWU)
(const_int 15)))))]
"TARGET_ZPN && TARGET_64BIT"
@@ -3144,12 +3144,12 @@
(vec_duplicate:VSHI
(vec_select:<VNHALF>
(match_operand:VSHI 1 "register_operand" " r, r, r, r, r, r, r, r")
(parallel [(match_operand:SI 4 "imm_0_1_operand" "v00, v00, v01, v01, v00, v00, v01, v01")])))
(parallel [(match_operand:SI 4 "imm_0_1_operand" "C00, C00, C01, C01, C00, C00, C01, C01")])))
(vec_duplicate:VSHI
(vec_select:<VNHALF>
(match_operand:VSHI 2 "register_operand" " r, r, r, r, r, r, r, r")
(parallel [(match_operand:SI 5 "imm_0_1_operand" "v00, v01, v01, v00, v00, v01, v01, v00")])))
(match_operand:SI 3 "imm_1_2_operand" "v01, v01, v01, v01, v02, v02, v02, v02")))]
(parallel [(match_operand:SI 5 "imm_0_1_operand" "C00, C01, C01, C00, C00, C01, C01, C00")])))
(match_operand:SI 3 "imm_1_2_operand" "C01, C01, C01, C01, C02, C02, C02, C02")))]
"TARGET_ZPN"
"@
pkbb<bits>\t%0, %2, %1
@@ -3803,11 +3803,11 @@
(sign_extend:DI
(vec_select:HI
(match_operand:V2HI 1 "register_operand" " r, r, r, r")
(parallel [(match_operand:SI 4 "imm_0_1_operand" " v00, v00, v01, v01")])))
(parallel [(match_operand:SI 4 "imm_0_1_operand" " C00, C00, C01, C01")])))
(sign_extend:DI
(vec_select:HI
(match_operand:V2HI 2 "register_operand" " r, r, r, r")
(parallel [(match_operand:SI 5 "imm_0_1_operand" " v00, v01, v01, v00")]))))))]
(parallel [(match_operand:SI 5 "imm_0_1_operand" " C00, C01, C01, C00")]))))))]
"TARGET_ZPSF && !TARGET_64BIT"
{
const char *pats[] = { "smalbb\t%0, %1, %2",
@@ -3873,20 +3873,20 @@
(sign_extend:DI
(vec_select:HI
(match_operand:V4HI 1 "register_operand" " r, r, r, r")
(parallel [(match_operand:SI 4 "imm_0_1_operand" " v00, v00, v01, v01")])))
(parallel [(match_operand:SI 4 "imm_0_1_operand" " C00, C00, C01, C01")])))
(sign_extend:DI
(vec_select:HI
(match_operand:V4HI 2 "register_operand" " r, r, r, r")
(parallel [(match_operand:SI 5 "imm_0_1_operand" " v00, v01, v01, v00")]))))
(parallel [(match_operand:SI 5 "imm_0_1_operand" " C00, C01, C01, C00")]))))
(mult:DI
(sign_extend:DI
(vec_select:HI
(match_dup 1)
(parallel [(match_operand:SI 6 "imm_2_3_operand" " v02, v02, v03, v03")])))
(parallel [(match_operand:SI 6 "imm_2_3_operand" " C02, C02, C03, C03")])))
(sign_extend:DI
(vec_select:HI
(match_dup 2)
(parallel [(match_operand:SI 7 "imm_2_3_operand" " v02, v03, v03, v02")])))))))]
(parallel [(match_operand:SI 7 "imm_2_3_operand" " C02, C03, C03, C02")])))))))]
"TARGET_ZPSF && TARGET_64BIT"
"@
smalbb\t%0, %1, %2
@@ -4523,10 +4523,10 @@
(sign_extend:SI
(vec_select:HI
(match_operand:V2HI 1 "register_operand" " r, r, r, r")
(parallel [(match_operand:SI 3 "imm_0_1_operand" " v00, v00, v01, v01")])))
(parallel [(match_operand:SI 3 "imm_0_1_operand" " C00, C00, C01, C01")])))
(sign_extend:SI (vec_select:HI
(match_operand:V2HI 2 "register_operand" " r, r, r, r")
(parallel [(match_operand:SI 4 "imm_0_1_operand" " v00, v01, v01, v00")])))))]
(parallel [(match_operand:SI 4 "imm_0_1_operand" " C00, C01, C01, C00")])))))]
"TARGET_ZPN && !TARGET_64BIT"
{
const char *pats[] = { "smbb16\t%0, %1, %2",
@@ -4581,13 +4581,13 @@
(sign_extend:V2SI
(vec_select:V2HI
(match_operand:V4HI 1 "register_operand" "r, r, r")
(parallel [(match_operand:SI 3 "imm2u_operand" " v00, v00, v01")
(match_operand:SI 4 "imm2u_operand" " v02, v02, v03")])))
(parallel [(match_operand:SI 3 "imm2u_operand" " C00, C00, C01")
(match_operand:SI 4 "imm2u_operand" " C02, C02, C03")])))
(sign_extend:V2SI
(vec_select:V2HI
(match_operand:V4HI 2 "register_operand" "r, r, r")
(parallel [(match_operand:SI 5 "imm2u_operand" " v00, v01, v01")
(match_operand:SI 6 "imm2u_operand" " v02, v03, v03")])))))]
(parallel [(match_operand:SI 5 "imm2u_operand" " C00, C01, C01")
(match_operand:SI 6 "imm2u_operand" " C02, C03, C03")])))))]
"TARGET_ZPN && TARGET_64BIT"
"@
smbb16\t%0, %1, %2
@@ -4639,10 +4639,10 @@
(sign_extend:DI
(vec_select:SI
(match_operand:V2SI 1 "register_operand" " r, r, r, r")
(parallel [(match_operand:SI 3 "imm_0_1_operand" " v00, v00, v01, v01")])))
(parallel [(match_operand:SI 3 "imm_0_1_operand" " C00, C00, C01, C01")])))
(sign_extend:DI (vec_select:SI
(match_operand:V2SI 2 "register_operand" " r, r, r, r")
(parallel [(match_operand:SI 4 "imm_0_1_operand" " v00, v01, v01, v00")])))))]
(parallel [(match_operand:SI 4 "imm_0_1_operand" " C00, C01, C01, C00")])))))]
"TARGET_ZPRV && TARGET_64BIT"
{
const char *pats[] = { "smbb32\t%0, %1, %2",
@@ -4969,7 +4969,7 @@
(sign_extend:DI
(vec_select:HI
(match_operand:V2HI 2 "register_operand" " r, r")
(parallel [(match_operand:SI 3 "imm_0_1_operand" "v00, v01")]))))
(parallel [(match_operand:SI 3 "imm_0_1_operand" "C00, C01")]))))
(const_int 16))))]
"TARGET_ZPN && !TARGET_64BIT"
{
@@ -5017,7 +5017,7 @@
(sign_extend:DI
(vec_select:HI
(match_operand:V4HI 2 "register_operand" " r, r")
(parallel [(match_operand:SI 3 "imm_0_1_operand" "v00, v01")]))))
(parallel [(match_operand:SI 3 "imm_0_1_operand" "C00, C01")]))))
(const_int 16)))
(truncate:SI
(lshiftrt:DI
@@ -5029,7 +5029,7 @@
(sign_extend:DI
(vec_select:HI
(match_dup 2)
(parallel [(match_operand:SI 4 "imm_2_3_operand" "v02, v03")]))))
(parallel [(match_operand:SI 4 "imm_2_3_operand" "C02, C03")]))))
(const_int 16)))))]
"TARGET_ZPN && TARGET_64BIT"
{
@@ -5072,7 +5072,7 @@
(sign_extend:DI
(vec_select:HI
(match_operand:V2HI 2 "register_operand" " r, r")
(parallel [(match_operand:SI 3 "imm_0_1_operand" " v00, v01")]))))]
(parallel [(match_operand:SI 3 "imm_0_1_operand" " C00, C01")]))))]
UNSPEC_ROUND)
(const_int 16))))]
"TARGET_ZPN && !TARGET_64BIT"
@@ -5121,7 +5121,7 @@
(sign_extend:DI
(vec_select:HI
(match_operand:V4HI 2 "register_operand" " r, r")
(parallel [(match_operand:SI 3 "imm_0_1_operand" "v00, v01")]))))]
(parallel [(match_operand:SI 3 "imm_0_1_operand" "C00, C01")]))))]
UNSPEC_ROUND)
(const_int 16)))
(truncate:SI
@@ -5135,7 +5135,7 @@
(sign_extend:DI
(vec_select:HI
(match_dup 2)
(parallel [(match_operand:SI 4 "imm_2_3_operand" "v02, v03")]))))]
(parallel [(match_operand:SI 4 "imm_2_3_operand" "C02, C03")]))))]
UNSPEC_ROUND)
(const_int 16)))))]
"TARGET_ZPN && TARGET_64BIT"
@@ -6600,22 +6600,22 @@
(sign_extend:SI
(vec_select:HI
(match_operand:V4HI 1 "register_operand" " r, r, r, r")
(parallel [(match_operand:SI 3 "imm_0_1_operand" " v00, v00, v01, v01")])))
(parallel [(match_operand:SI 3 "imm_0_1_operand" " C00, C00, C01, C01")])))
(sign_extend:SI
(vec_select:HI
(match_operand:V4HI 2 "register_operand" " r, r, r, r")
(parallel [(match_operand:SI 4 "imm_0_1_operand" " v00, v01, v01, v00")]))))
(parallel [(match_operand:SI 4 "imm_0_1_operand" " C00, C01, C01, C00")]))))
(const_int 1))
(ashift:SI
(mult:SI
(sign_extend:SI
(vec_select:HI
(match_dup 1)
(parallel [(match_operand:SI 5 "imm_2_3_operand" " v02, v02, v03, v03")])))
(parallel [(match_operand:SI 5 "imm_2_3_operand" " C02, C02, C03, C03")])))
(sign_extend:SI
(vec_select:HI
(match_dup 2)
(parallel [(match_operand:SI 6 "imm_2_3_operand" " v02, v03, v03, v02")]))))
(parallel [(match_operand:SI 6 "imm_2_3_operand" " C02, C03, C03, C02")]))))
(const_int 1)))
(match_operand:V2SI 7 "register_operand" " 0, 0, 0, 0")))]
"TARGET_ZPRV && TARGET_64BIT"
@@ -6706,11 +6706,11 @@
(sign_extend:DI
(vec_select:SI
(match_operand:V2SI 1 "register_operand" " r, r, r, r")
(parallel [(match_operand:SI 3 "imm_0_1_operand" " v00, v00, v01, v01")])))
(parallel [(match_operand:SI 3 "imm_0_1_operand" " C00, C00, C01, C01")])))
(sign_extend:DI
(vec_select:SI
(match_operand:V2SI 2 "register_operand" " r, r, r, r")
(parallel [(match_operand:SI 4 "imm_0_1_operand" " v00, v01, v01, v00")]))))
(parallel [(match_operand:SI 4 "imm_0_1_operand" " C00, C01, C01, C00")]))))
(match_operand:DI 5 "register_operand" " 0, 0, 0, 0")))]
"TARGET_ZPRV && TARGET_64BIT"
"@
@@ -6987,7 +6987,7 @@
(sign_extend:DI
(vec_select:HI
(match_operand:V4HI 2 "register_operand" " r, r")
(parallel [(match_operand:SI 3 "imm_0_1_operand" "v00, v01")]))))]
(parallel [(match_operand:SI 3 "imm_0_1_operand" "C00, C01")]))))]
UNSPEC_KMMW)
(const_int 15)))
(truncate:SI
@@ -7000,7 +7000,7 @@
(sign_extend:DI
(vec_select:HI
(match_dup 2)
(parallel [(match_operand:SI 4 "imm_2_3_operand" "v02, v03")]))))]
(parallel [(match_operand:SI 4 "imm_2_3_operand" "C02, C03")]))))]
UNSPEC_KMMW)
(const_int 15)))))]
"TARGET_ZPN && TARGET_64BIT"
@@ -7040,7 +7040,7 @@
(sign_extend:DI
(vec_select:HI
(match_operand:V2HI 2 "register_operand" " r, r")
(parallel [(match_operand:SI 3 "imm_0_1_operand" " v00, v01")]))))]
(parallel [(match_operand:SI 3 "imm_0_1_operand" " C00, C01")]))))]
UNSPEC_KMMW)
(const_int 15))))]
"TARGET_ZPN && !TARGET_64BIT"

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