[fix] Fix wrong type in builtin & add missing intrinsic

riscvarchive · May 14, 2021 · 83e60d0 · 83e60d0
1 parent ecd8198
commit 83e60d0
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Showing 2 changed files with 6 additions and 4 deletions.
diff --git a/gcc/config/riscv/riscv-builtins-rvp.def b/gcc/config/riscv/riscv-builtins-rvp.def
@@ -81,8 +81,8 @@ RVP_DIRECT_BUILTIN (cmpeqv2hi, cmpeq16, RISCV_UIXLEN_FTYPE_UIXLEN_UIXLEN, zpn32)
 RVP_DIRECT_BUILTIN (cmpeqv4hi, cmpeq16, RISCV_UIXLEN_FTYPE_UIXLEN_UIXLEN, zpn64),
 RVP_DIRECT_BUILTIN (cmpeqv2hi, v_scmpeq16, RISCV_UV2HI_FTYPE_V2HI_V2HI, zpn32),
 RVP_DIRECT_BUILTIN (cmpeqv2hi, v_ucmpeq16, RISCV_UV2HI_FTYPE_UV2HI_UV2HI, zpn32),
-RVP_DIRECT_BUILTIN (cmpeqv4hi, v64_scmpeq16, RISCV_UIXLEN_FTYPE_V4HI_V4HI, zpn64),
-RVP_DIRECT_BUILTIN (cmpeqv4hi, v64_ucmpeq16, RISCV_UIXLEN_FTYPE_UV4HI_UV4HI, zpn64),
+RVP_DIRECT_BUILTIN (cmpeqv4hi, v64_scmpeq16, RISCV_UV4HI_FTYPE_V4HI_V4HI, zpn64),
+RVP_DIRECT_BUILTIN (cmpeqv4hi, v64_ucmpeq16, RISCV_UV4HI_FTYPE_UV4HI_UV4HI, zpn64),
 RVP_DIRECT_BUILTIN (crasv2hi, cras16, RISCV_UIXLEN_FTYPE_UIXLEN_UIXLEN, zpn32),
 RVP_DIRECT_BUILTIN (crasv2hi, v_ucras16, RISCV_UV2HI_FTYPE_UV2HI_UV2HI, zpn32),
 RVP_DIRECT_BUILTIN (crasv2hi, v_scras16, RISCV_V2HI_FTYPE_V2HI_V2HI, zpn32),
@@ -889,7 +889,7 @@ RVP_DIRECT_BUILTIN (ursubv2si3, v64_ursub32, RISCV_UV2SI_FTYPE_UV2SI_UV2SI, zprv
 RVP_DIRECT_BUILTIN (smal, v_smal, RISCV_LLONG_FTYPE_LLONG_V2HI, zpsf32),
 RVP_DIRECT_BUILTIN (smal_64, v64_smal, RISCV_LLONG_FTYPE_LLONG_V4HI, zpsf64),
 RVP_DIRECT_BUILTIN (smal, smal, RISCV_LLONG_FTYPE_LLONG_UIXLEN, zpsf32),
-RVP_DIRECT_BUILTIN (smal_64, smal, RISCV_LLONG_FTYPE_LLONG_V2HI, zpsf64),
+RVP_DIRECT_BUILTIN (smal_64, smal, RISCV_LLONG_FTYPE_LLONG_V4HI, zpsf64),
 RVP_DIRECT_BUILTIN (dsp_adddi3, sadd64, RISCV_LLONG_FTYPE_LLONG_LLONG, zpsf32),
 RVP_DIRECT_BUILTIN (dsp_adddi3, uadd64, RISCV_ULLONG_FTYPE_ULLONG_ULLONG, zpsf32),
 RVP_DIRECT_BUILTIN (adddi3, sadd64, RISCV_LLONG_FTYPE_LLONG_LLONG, zpsf64),
@@ -961,7 +961,7 @@ RVP_DIRECT_BUILTIN (smalds64, v64_smalds, RISCV_LLONG_FTYPE_LLONG_V4HI_V4HI, zps
 RVP_DIRECT_BUILTIN (smaldrs64, v64_smaldrs, RISCV_LLONG_FTYPE_LLONG_V4HI_V4HI, zpsf64),
 RVP_DIRECT_BUILTIN (smalxds64, v64_smalxds, RISCV_LLONG_FTYPE_LLONG_V4HI_V4HI, zpsf64),
 RVP_DIRECT_BUILTIN (smslxda1, smslxda, RISCV_LLONG_FTYPE_LLONG_UIXLEN_UIXLEN, zpsf32),
-RVP_DIRECT_BUILTIN (smslxda64, smslxda, RISCV_LLONG_FTYPE_LLONG_V4HI_V4HI, zpsf64),
+RVP_DIRECT_BUILTIN (smslxda64, smslxda, RISCV_LLONG_FTYPE_LLONG_UIXLEN_UIXLEN, zpsf64),
 RVP_DIRECT_BUILTIN (smslxda1, v_smslxda, RISCV_LLONG_FTYPE_LLONG_V2HI_V2HI, zpsf32),
 RVP_DIRECT_BUILTIN (smslxda64, v64_smslxda, RISCV_LLONG_FTYPE_LLONG_V4HI_V4HI, zpsf64),
 RVP_DIRECT_BUILTIN (umulsidi3, mulr64, RISCV_UDI_FTYPE_USI_USI, zpsf),

diff --git a/gcc/config/riscv/rvp_intrinsic.h b/gcc/config/riscv/rvp_intrinsic.h
@@ -1602,6 +1602,7 @@ typedef unsigned int uint32x4_t __attribute__((vector_size(16)));
 #endif
 
 // ZPN subext intrinsics for both RV32 & RV64
+#define __rv__swap16 __riscv__swap16
 #define __rv__add16 __riscv__add16
 #define __rv__radd16 __riscv__radd16
 #define __rv__uradd16 __riscv__uradd16
@@ -1960,6 +1961,7 @@ typedef unsigned int uint32x4_t __attribute__((vector_size(16)));
 #define __rv__v_smmwb_u __riscv__v_smmwb_u
 #define __rv__v_smmwt __riscv__v_smmwt
 #define __rv__v_smmwt_u __riscv__v_smmwt_u
+#define __rv__v_swap16 __riscv__v_swap16
 #if __riscv_xlen == 64
 // RV64 Only ZPN vector intrinsic
 #define __rv__v_smmul __riscv__v_smmul