[crypto] Add testcase and some fix

Co-authored-by: Shihua Liao <[email protected]>
Co-authored-by: Jiawei Chen <[email protected]>

gcc/common/config/riscv/riscv-common.c

@@ -58,6 +58,8 @@ struct riscv_implied_info_t
 riscv_implied_info_t riscv_implied_info[] =
 {
   {"d", "f"},
+  {"f", "zicsr"},
+  {"d", "zicsr"},
   {"k", "zkn"},
   {"k", "zkr"},
   {"zkn", "zkne"},
@@ -120,6 +122,18 @@ static const struct riscv_ext_version riscv_ext_version_table[] =
   {"zifencei", ISA_SPEC_CLASS_20191213, 2, 0},
   {"zifencei", ISA_SPEC_CLASS_20190608, 2, 0},
 
+  {"k",    ISA_SPEC_CLASS_NONE, 0, 90},
+  {"zkb",  ISA_SPEC_CLASS_NONE, 0, 90},
+  {"zkg",  ISA_SPEC_CLASS_NONE, 0, 90},
+  {"zkn",  ISA_SPEC_CLASS_NONE, 0, 90},
+  {"zkne", ISA_SPEC_CLASS_NONE, 0, 90},
+  {"zknd", ISA_SPEC_CLASS_NONE, 0, 90},
+  {"zknh", ISA_SPEC_CLASS_NONE, 0, 90},
+  {"zkr",  ISA_SPEC_CLASS_NONE, 0, 90},
+  {"zks",  ISA_SPEC_CLASS_NONE, 0, 90},
+  {"zksed",ISA_SPEC_CLASS_NONE, 0, 90},
+  {"zksh", ISA_SPEC_CLASS_NONE, 0, 90},
+
   /* Terminate the list.  */
   {NULL, ISA_SPEC_CLASS_NONE, 0, 0}
 };
@@ -967,6 +981,9 @@ static const riscv_ext_flag_table_t riscv_ext_flag_table[] =
   {"d", &gcc_options::x_target_flags, MASK_DOUBLE_FLOAT},
   {"c", &gcc_options::x_target_flags, MASK_RVC},
 
+  {"zicsr",    &gcc_options::x_riscv_zi_subext, MASK_ZICSR},
+  {"zifencei", &gcc_options::x_riscv_zi_subext, MASK_ZIFENCEI},
+
   {"zkg", &gcc_options::x_riscv_crypto_subext, MASK_ZKG},
   {"zkb", &gcc_options::x_riscv_crypto_subext, MASK_ZKB},
   {"zkr", &gcc_options::x_riscv_crypto_subext, MASK_ZKR},

gcc/config/riscv/crypto.md

@@ -24,13 +24,17 @@
   UNSPEC_AES_DSM
   UNSPEC_AES_ES
   UNSPEC_AES_ESM
-  UNSPEC_AES_K
+  UNSPEC_AES_IM
+  UNSPEC_AES_KS1
+  UNSPEC_AES_KS2
   UNSPEC_SHA_256_SIG0
   UNSPEC_SHA_256_SIG1
   UNSPEC_SHA_256_SUM0
   UNSPEC_SHA_256_SUM1
   UNSPEC_SHA_512_SIG0
+  UNSPEC_SHA_512_SIG0_2
   UNSPEC_SHA_512_SIG1
+  UNSPEC_SHA_512_SIG1_2
   UNSPEC_SHA_512_SUM0
   UNSPEC_SHA_512_SUM1
   UNSPEC_SM3_P0
@@ -114,23 +118,23 @@
 (define_insn "riscv_aes64im"
   [(set (match_operand:DI 0 "register_operand" "=r")
         (unspec:DI [(match_operand:DI 1 "register_operand" "r")]
-                   UNSPEC_AES_K))]
+                   UNSPEC_AES_IM))]
   "TARGET_ZKND && TARGET_64BIT"
   "aes64im\t%0,%1")
 
 (define_insn "riscv_aes64ks1i"
   [(set (match_operand:DI 0 "register_operand" "=r")
         (unspec:DI [(match_operand:DI 1 "register_operand" "r")
                    (match_operand:DI 2 "immediate_operand" "")]
-                   UNSPEC_AES_K))]
+                   UNSPEC_AES_KS1))]
   "TARGET_ZKNE && TARGET_64BIT"
   "aes64ks1i\t%0,%1,%2")
 
 (define_insn "riscv_aes64ks2"
   [(set (match_operand:DI 0 "register_operand" "=r")
         (unspec:DI [(match_operand:DI 1 "register_operand" "r")
                    (match_operand:DI 2 "register_operand" "r")]
-                   UNSPEC_AES_K))]
+                   UNSPEC_AES_KS2))]
   "TARGET_ZKNE && TARGET_64BIT"
   "aes64ks2\t%0,%1,%2")
 
@@ -180,7 +184,7 @@
   [(set (match_operand:SI 0 "register_operand" "=r")
         (unspec:SI [(match_operand:SI 1 "register_operand" "r")
                    (match_operand:SI 2 "register_operand" "r")]
-                   UNSPEC_SHA_512_SIG0))]
+                   UNSPEC_SHA_512_SIG0_2))]
   "TARGET_ZKNH && !TARGET_64BIT"
   "sha512sig0l\t%0,%1,%2")
 
@@ -196,7 +200,7 @@
   [(set (match_operand:SI 0 "register_operand" "=r")
         (unspec:SI [(match_operand:SI 1 "register_operand" "r")
                    (match_operand:SI 2 "register_operand" "r")]
-                   UNSPEC_SHA_512_SIG1))]
+                   UNSPEC_SHA_512_SIG1_2))]
   "TARGET_ZKNH && !TARGET_64BIT"
   "sha512sig1l\t%0,%1,%2")
 
@@ -212,7 +216,7 @@
   [(set (match_operand:SI 0 "register_operand" "=r")
         (unspec:SI [(match_operand:SI 1 "register_operand" "r")
                    (match_operand:SI 2 "register_operand" "r")]
-                   UNSPEC_SHA_512_SUM0))]
+                   UNSPEC_SHA_512_SUM1))]
   "TARGET_ZKNH && !TARGET_64BIT"
   "sha512sum1r\t%0,%1,%2")
 

gcc/config/riscv/multilib-generator

@@ -56,6 +56,19 @@ LONG_EXT_PREFIXES = ['z', 's', 'h', 'x']
 #
 IMPLIED_EXT = {
   "d" : ["f"],
+  "f" : ["zicsr"],
+  "f" : ["zifencei"],
+  "k" : ["zkn"],
+  "k" : ["zkr"],
+  "zkn" : ["zkne"],
+  "zkn" : ["zknd"],
+  "zkn" : ["zknh"],
+  "zkn" : ["zkg"],
+  "zkn" : ["zkb"],
+  "zks" : ["zksed"],
+  "zks" : ["zksh"],
+  "zks" : ["zkg"],
+  "zks" : ["zkb"],
 }
 
 def arch_canonicalize(arch):

gcc/config/riscv/riscv-builtins-crypto.def

@@ -51,10 +51,10 @@ DIRECT_BUILTIN (sha512sum0r, RISCV_SI_FTYPE_SI_SI, crypto_zknh32),
 DIRECT_BUILTIN (sha512sum1r, RISCV_SI_FTYPE_SI_SI, crypto_zknh32),
 
 // Zknh - SHA512 (RV64)
-DIRECT_BUILTIN (sha512sig0, RISCV_DI_FTYPE_DI_DI, crypto_zknh64),
-DIRECT_BUILTIN (sha512sig1, RISCV_DI_FTYPE_DI_DI, crypto_zknh64),
-DIRECT_BUILTIN (sha512sum0, RISCV_DI_FTYPE_DI_DI, crypto_zknh64),
-DIRECT_BUILTIN (sha512sum1, RISCV_DI_FTYPE_DI_DI, crypto_zknh64),
+DIRECT_BUILTIN (sha512sig0, RISCV_DI_FTYPE_DI, crypto_zknh64),
+DIRECT_BUILTIN (sha512sig1, RISCV_DI_FTYPE_DI, crypto_zknh64),
+DIRECT_BUILTIN (sha512sum0, RISCV_DI_FTYPE_DI, crypto_zknh64),
+DIRECT_BUILTIN (sha512sum1, RISCV_DI_FTYPE_DI, crypto_zknh64),
 
 // Zksh - SM3
 RISCV_BUILTIN (sm3p0_si, "sm3p0", RISCV_BUILTIN_DIRECT, RISCV_SI_FTYPE_SI, crypto_zksh32),

gcc/config/riscv/riscv-opts.h

@@ -61,15 +61,19 @@ enum riscv_align_data {
   riscv_align_data_type_natural
 };
 
-#define MASK_ZKG (1 << 0)
-#define MASK_ZKB (1 << 1)
-#define MASK_ZKR (1 << 2)
-#define MASK_ZKNE (1 << 3)
-#define MASK_ZKND (1 << 4)
-#define MASK_ZKNH (1 << 5)
-#define MASK_ZKSED (1 << 6)
-#define MASK_ZKSH (1 << 7)
+#define MASK_ZICSR    (1 << 0)
+#define MASK_ZIFENCEI (1 << 1)
+#define MASK_ZKG      (1 << 2)
+#define MASK_ZKB      (1 << 3)
+#define MASK_ZKR      (1 << 4)
+#define MASK_ZKNE     (1 << 5)
+#define MASK_ZKND     (1 << 6)
+#define MASK_ZKNH     (1 << 7)
+#define MASK_ZKSED    (1 << 8)
+#define MASK_ZKSH     (1 << 9)
 
+#define TARGET_ZICSR    ((riscv_zi_subext & MASK_ZICSR) != 0)
+#define TARGET_ZIFENCEI ((riscv_zi_subext & MASK_ZIFENCEI) != 0)
 #define TARGET_ZKG ((riscv_crypto_subext & MASK_ZKG) != 0)
 #define TARGET_ZKB ((riscv_crypto_subext & MASK_ZKB) != 0)
 #define TARGET_ZKR ((riscv_crypto_subext & MASK_ZKR) != 0)

gcc/config/riscv/riscv.md

@@ -1538,14 +1538,15 @@
 		     LCT_NORMAL, VOIDmode, operands[0], Pmode,
 		     operands[1], Pmode, const0_rtx, Pmode);
 #else
-  emit_insn (gen_fence_i ());
+  if (TARGET_ZIFENCEI)
+    emit_insn (gen_fence_i ());
 #endif
   DONE;
 })
 
 (define_insn "fence"
   [(unspec_volatile [(const_int 0)] UNSPECV_FENCE)]
-  ""
+  "TARGET_ZIFENCEI"
   "%|fence%-")
 
 (define_insn "fence_i"

gcc/testsuite/gcc.target/riscv/Zknd-aes-01.c

@@ -0,0 +1,15 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv32gc_zknd -mabi=ilp32 -O2" } */
+
+int foo1(int rs1)
+{
+    return __builtin_riscv_aes32dsi(rs1, 1);
+}
+
+int foo2(int rs1)
+{
+    return __builtin_riscv_aes32dsmi(rs1, 0);
+}
+
+/* { dg-final { scan-assembler-times "aes32dsi" 1 } } */
+/* { dg-final { scan-assembler-times "aes32dsmi" 1 } } */

gcc/testsuite/gcc.target/riscv/Zknd-aes-02.c

@@ -0,0 +1,21 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gc_zknd -mabi=lp64 -O2" } */
+
+long foo1(long rs1, long rs2)
+{
+    return __builtin_riscv_aes64ds(rs1, rs2);
+}
+
+long foo2(long rs1, long rs2)
+{
+    return __builtin_riscv_aes64dsm(rs1, rs2);
+}
+
+long foo3(long rs1)
+{
+    return __builtin_riscv_aes64im(rs1);
+}
+
+/* { dg-final { scan-assembler-times "aes64ds" 2 } } */
+/* { dg-final { scan-assembler-times "aes64dsm" 1 } } */
+/* { dg-final { scan-assembler-times "aes64im" 1 } } */

gcc/testsuite/gcc.target/riscv/Zkne-aes-01.c

@@ -0,0 +1,15 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv32gc_zkne -mabi=ilp32 -O2" } */
+
+int foo1(int rs1)
+{
+    return __builtin_riscv_aes32esi(rs1, 1);
+}
+
+int foo2(int rs1)
+{
+    return __builtin_riscv_aes32esmi(rs1, 1);
+}
+
+/* { dg-final { scan-assembler-times "aes32esi" 1 } } */
+/* { dg-final { scan-assembler-times "aes32esmi" 1 } } */

gcc/testsuite/gcc.target/riscv/Zkne-aes-02.c

@@ -0,0 +1,27 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gc_zkne -mabi=lp64 -O2" } */
+
+long foo1(long rs1, long rs2)
+{
+    return __builtin_riscv_aes64es(rs1, rs2);
+}
+
+long foo2(long rs1, long rs2)
+{
+    return __builtin_riscv_aes64esm(rs1, rs2);
+}
+
+long foo3(long rs1)
+{
+    return __builtin_riscv_aes64ks1i(rs1, 1);
+}
+
+long foo4(long rs1, long rs2)
+{
+    return __builtin_riscv_aes64ks2(rs1, rs2);
+}
+
+/* { dg-final { scan-assembler-times "aes64es" 2 } } */
+/* { dg-final { scan-assembler-times "aes64esm" 1 } } */
+/* { dg-final { scan-assembler-times "aes64ks1i" 1 } } */
+/* { dg-final { scan-assembler-times "aes64ks2" 1 } } */

gcc/testsuite/gcc.target/riscv/Zknh-sha256.c

@@ -0,0 +1,27 @@
+/* { dg-do compile { target { riscv64*-*-* } } } */
+/* { dg-options "-march=rv64gc_zknh -mabi=lp64 -O2" } */
+
+long foo1(long rs1)
+{
+    return __builtin_riscv_sha256sig0(rs1);
+}
+
+long foo2(long rs1)
+{
+    return __builtin_riscv_sha256sig1(rs1);
+}
+
+long foo3(long rs1)
+{
+    return __builtin_riscv_sha256sum0(rs1);
+}
+
+long foo4(long rs1)
+{
+    return __builtin_riscv_sha256sum1(rs1);
+}
+
+/* { dg-final { scan-assembler-times "sha256sig0" 1 } } */
+/* { dg-final { scan-assembler-times "sha256sig1" 1 } } */
+/* { dg-final { scan-assembler-times "sha256sum0" 1 } } */
+/* { dg-final { scan-assembler-times "sha256sum1" 1 } } */

gcc/testsuite/gcc.target/riscv/Zknh-sha512-01.c

@@ -0,0 +1,40 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv32gc_zknh -mabi=ilp32 -O2" } */
+
+int foo1(int rs1, int rs2)
+{
+    return __builtin_riscv_sha512sig0h(rs1, rs2);
+}
+
+int foo2(int rs1, int rs2)
+{
+    return __builtin_riscv_sha512sig0l(rs1, rs2);
+}
+
+int foo3(int rs1, int rs2)
+{
+    return __builtin_riscv_sha512sig1h(rs1, rs2);
+}
+
+int foo4(int rs1, int rs2)
+{
+    return __builtin_riscv_sha512sig1l(rs1, rs2);
+}
+
+int foo5(int rs1, int rs2)
+{
+    return __builtin_riscv_sha512sum0r(rs1, rs2);
+}
+
+int foo6(int rs1, int rs2)
+{
+    return __builtin_riscv_sha512sum1r(rs1, rs2);
+}
+
+/* { dg-final { scan-assembler-times "sha512sig0h" 1 } } */
+/* { dg-final { scan-assembler-times "sha512sig0l" 1 } } */
+/* { dg-final { scan-assembler-times "sha512sig1h" 1 } } */
+/* { dg-final { scan-assembler-times "sha512sig1l" 1 } } */
+/* { dg-final { scan-assembler-times "sha512sum0r" 1 } } */
+/* { dg-final { scan-assembler-times "sha512sum1r" 1 } } */
+

gcc/testsuite/gcc.target/riscv/Zknh-sha512-02.c

@@ -0,0 +1,28 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64i_zknh -mabi=lp64 -O2" } */
+
+long foo1(long rs1)
+{
+    return __builtin_riscv_sha512sig0(rs1);
+}
+
+long foo2(long rs1)
+{
+    return __builtin_riscv_sha512sig1(rs1);
+}
+
+
+long foo3(long rs1)
+{
+    return __builtin_riscv_sha512sum0(rs1);
+}
+
+long foo4(long rs1)
+{
+    return __builtin_riscv_sha512sum1(rs1);
+}
+
+/* { dg-final { scan-assembler-times "sha512sig0" 1 } } */
+/* { dg-final { scan-assembler-times "sha512sig1" 1 } } */
+/* { dg-final { scan-assembler-times "sha512sum0" 1 } } */
+/* { dg-final { scan-assembler-times "sha512sum1" 1 } } */

gcc/testsuite/gcc.target/riscv/Zkr-pollentropy.c

@@ -0,0 +1,15 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gc_zkr -mabi=lp64 -O2" } */
+
+long foo1()
+{
+    return __builtin_riscv_pollentropy();
+}
+
+long foo2()
+{
+    return __builtin_riscv_getnoise();
+}
+
+/* { dg-final { scan-assembler-times "pollentropy" 2 } } */
+/* { dg-final { scan-assembler-times "getnoise" 1 } } */