incorporate new type changes

riscv · Dec 21, 2024 · fb13ad0 · fb13ad0
1 parent 40ad532
commit fb13ad0
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Showing 7 changed files with 29 additions and 29 deletions.
diff --git a/c_emulator/riscv_sim_RV64 b/c_emulator/riscv_sim_RV64
diff --git a/model/riscv_insts_aext.sail b/model/riscv_insts_aext.sail
@@ -86,7 +86,7 @@ function clause execute(LOADRES(aq, rl, rs1, width, rd)) = {
       /* "LR faults like a normal load, even though it's in the AMO major opcode space."
         * - Andrew Waterman, isa-dev, 10 Jul 2018.
         */
-      if (instrDataMatch(cur_privilege, zero_extend(vaddr), zero_extend(0b0), matchSize_of_wordWidth(width), LOAD_MATCH_BEFORE))
+      if (instrDataMatch(cur_privilege, virtaddr_bits(vaddr), zero_extend(0b0), matchSize_of_wordWidth(width), LOAD_MATCH_BEFORE))
       then { RETIRE_FAIL }
       else if not(is_aligned(virtaddr_bits(vaddr), width))
       then { handle_mem_exception(vaddr, E_Load_Addr_Align()); RETIRE_FAIL }
@@ -97,7 +97,7 @@ function clause execute(LOADRES(aq, rl, rs1, width, rd)) = {
             MemValue(result) => { 
               load_reservation(physaddr_bits(addr));
               X(rd) = sign_extend(result); 
-              let load_after_match : bool = instrDataMatch(cur_privilege, zero_extend(vaddr), zero_extend(X(rd)), matchSize_of_wordWidth(width), LOAD_MATCH_AFTER);
+              let load_after_match : bool = instrDataMatch(cur_privilege, virtaddr_bits(vaddr), zero_extend(X(rd)), matchSize_of_wordWidth(width), LOAD_MATCH_AFTER);
               RETIRE_SUCCESS
             },
             MemException(e)  => { handle_mem_exception(vaddr, e); RETIRE_FAIL }
@@ -139,7 +139,7 @@ function clause execute (STORECON(aq, rl, rs2, rs1, width, rd)) = {
     match ext_data_get_addr(rs1, zeros(), Write(Data), width_bytes) {
       Ext_DataAddr_Error(e)  => { ext_handle_data_check_error(e); RETIRE_FAIL },
       Ext_DataAddr_OK(vaddr) => {
-        if (instrDataMatch(cur_privilege, zero_extend(vaddr), zero_extend(dbg_store_data[width_bytes * 8 - 1 .. 0]), matchSize_of_wordWidth(width), STORE_MATCH))
+        if (instrDataMatch(cur_privilege, virtaddr_bits(vaddr), zero_extend(dbg_store_data[width_bytes * 8 - 1 .. 0]), matchSize_of_wordWidth(width), STORE_MATCH))
         then { RETIRE_FAIL }
         else if not(is_aligned(virtaddr_bits(vaddr), width))
         then { handle_mem_exception(vaddr, E_SAMO_Addr_Align()); RETIRE_FAIL }

diff --git a/model/riscv_insts_base.sail b/model/riscv_insts_base.sail
@@ -334,7 +334,7 @@ function clause execute(LOAD(imm, rs1, rd, is_unsigned, width, aq, rl)) = {
   match ext_data_get_addr(rs1, offset, Read(Data), width_bytes) {
     Ext_DataAddr_Error(e)  => { ext_handle_data_check_error(e); RETIRE_FAIL },
     Ext_DataAddr_OK(vaddr) => {
-      if (instrDataMatch(cur_privilege, zero_extend(vaddr), zero_extend(0b0), matchSize_of_wordWidth(width), LOAD_MATCH_BEFORE))
+      if (instrDataMatch(cur_privilege, virtaddr_bits(vaddr), zero_extend(0b0), matchSize_of_wordWidth(width), LOAD_MATCH_BEFORE))
       then { RETIRE_FAIL }
       else if check_misaligned(vaddr, width)
       then { handle_mem_exception(vaddr, E_Load_Addr_Align()); RETIRE_FAIL }
@@ -345,7 +345,7 @@ function clause execute(LOAD(imm, rs1, rd, is_unsigned, width, aq, rl)) = {
           match mem_read(Read(Data), paddr, width_bytes, aq, rl, false) {
             MemValue(result) => {
               X(rd) = extend_value(is_unsigned, result);
-              let load_after_match : bool = instrDataMatch(cur_privilege, zero_extend(vaddr), zero_extend(X(rd)), matchSize_of_wordWidth(width), LOAD_MATCH_AFTER);
+              let load_after_match : bool = instrDataMatch(cur_privilege, virtaddr_bits(vaddr), zero_extend(X(rd)), matchSize_of_wordWidth(width), LOAD_MATCH_AFTER);
               RETIRE_SUCCESS
             },
             MemException(e) => { handle_mem_exception(vaddr, e); RETIRE_FAIL },
@@ -397,7 +397,7 @@ function clause execute (STORE(imm, rs2, rs1, width, aq, rl)) = {
   match ext_data_get_addr(rs1, offset, Write(Data), width_bytes) {
     Ext_DataAddr_Error(e)  => { ext_handle_data_check_error(e); RETIRE_FAIL },
     Ext_DataAddr_OK(vaddr) =>
-      if (instrDataMatch(cur_privilege, zero_extend(vaddr), zero_extend(dbg_store_data[width_bytes * 8 - 1 .. 0]), matchSize_of_wordWidth(width), STORE_MATCH))
+      if (instrDataMatch(cur_privilege, virtaddr_bits(vaddr), zero_extend(dbg_store_data[width_bytes * 8 - 1 .. 0]), matchSize_of_wordWidth(width), STORE_MATCH))
       then { RETIRE_FAIL }
       else if check_misaligned(vaddr, width)
       then { handle_mem_exception(vaddr, E_SAMO_Addr_Align()); RETIRE_FAIL }

diff --git a/model/riscv_insts_vext_mem.sail b/model/riscv_insts_vext_mem.sail
@@ -91,7 +91,7 @@ function process_vlseg (nf, vm, vd, load_width_bytes, rs1, EMUL_pow, num_elem) =
         match ext_data_get_addr(rs1, to_bits(xlen, elem_offset), Read(Data), load_width_bytes) {
           Ext_DataAddr_Error(e)  => { ext_handle_data_check_error(e); return RETIRE_FAIL },
           Ext_DataAddr_OK(vaddr) =>
-              if (instrDataMatch(cur_privilege, zero_extend(vaddr), zero_extend(0b0), matchSize_of_wordWidth(width_type), LOAD_MATCH_BEFORE))
+              if (instrDataMatch(cur_privilege, virtaddr_bits(vaddr), zero_extend(0b0), matchSize_of_wordWidth(width_type), LOAD_MATCH_BEFORE))
               then { return RETIRE_FAIL }
               else if check_misaligned(vaddr, width_type)
               then { handle_mem_exception(vaddr, E_Load_Addr_Align()); return RETIRE_FAIL }
@@ -101,7 +101,7 @@ function process_vlseg (nf, vm, vd, load_width_bytes, rs1, EMUL_pow, num_elem) =
                   match mem_read(Read(Data), paddr, load_width_bytes, false, false, false) {
                     MemValue(elem)   => {
                       if (xlen_bytes >= load_width_bytes) then {
-                        let load_after_match : bool = instrDataMatch(cur_privilege, zero_extend(vaddr), zero_extend(elem), matchSize_of_wordWidth(width_type), LOAD_MATCH_AFTER);
+                        let load_after_match : bool = instrDataMatch(cur_privilege, virtaddr_bits(vaddr), zero_extend(elem), matchSize_of_wordWidth(width_type), LOAD_MATCH_AFTER);
                       };
                       write_single_element(load_width_bytes * 8, i, vd + to_bits(5, j * EMUL_reg), elem)
                     },
@@ -173,7 +173,7 @@ function process_vlsegff (nf, vm, vd, load_width_bytes, rs1, EMUL_pow, num_elem)
               }
             },
             Ext_DataAddr_OK(vaddr) => {
-              if (instrDataMatch(cur_privilege, zero_extend(vaddr), zero_extend(0b0), matchSize_of_wordWidth(width_type), LOAD_MATCH_BEFORE))
+              if (instrDataMatch(cur_privilege, virtaddr_bits(vaddr), zero_extend(0b0), matchSize_of_wordWidth(width_type), LOAD_MATCH_BEFORE))
               then { return RETIRE_FAIL }
               else if check_misaligned(vaddr, width_type) then {
                 if i == 0 then { handle_mem_exception(vaddr, E_Load_Addr_Align()); return RETIRE_FAIL }
@@ -195,7 +195,7 @@ function process_vlsegff (nf, vm, vd, load_width_bytes, rs1, EMUL_pow, num_elem)
                   match mem_read(Read(Data), paddr, load_width_bytes, false, false, false) {
                     MemValue(elem)   => {
                       if (xlen_bytes >= load_width_bytes) then {
-                        let load_after_match : bool = instrDataMatch(cur_privilege, zero_extend(vaddr), zero_extend(elem), matchSize_of_wordWidth(width_type), LOAD_MATCH_AFTER);
+                        let load_after_match : bool = instrDataMatch(cur_privilege, virtaddr_bits(vaddr), zero_extend(elem), matchSize_of_wordWidth(width_type), LOAD_MATCH_AFTER);
                       };
                       write_single_element(load_width_bytes * 8, i, vd + to_bits(5, j * EMUL_reg), elem)
                     },
@@ -278,7 +278,7 @@ function process_vsseg (nf, vm, vs3, load_width_bytes, rs1, EMUL_pow, num_elem)
           Ext_DataAddr_Error(e)  => { ext_handle_data_check_error(e); return RETIRE_FAIL },
           Ext_DataAddr_OK(vaddr) => {
             if (xlen_bytes >= load_width_bytes) then {
-              trigMatched = instrDataMatch(cur_privilege, zero_extend(vaddr), zero_extend(dbg_elem_val), matchSize_of_wordWidth(width_type), STORE_MATCH);
+              trigMatched = instrDataMatch(cur_privilege, virtaddr_bits(vaddr), zero_extend(dbg_elem_val), matchSize_of_wordWidth(width_type), STORE_MATCH);
             };
             if (trigMatched)
             then { return RETIRE_FAIL }
@@ -354,7 +354,7 @@ function process_vlsseg (nf, vm, vd, load_width_bytes, rs1, rs2, EMUL_pow, num_e
         match ext_data_get_addr(rs1, to_bits(xlen, elem_offset), Read(Data), load_width_bytes) {
           Ext_DataAddr_Error(e)  => { ext_handle_data_check_error(e); return RETIRE_FAIL },
           Ext_DataAddr_OK(vaddr) =>
-            if (instrDataMatch(cur_privilege, zero_extend(vaddr), zero_extend(0b0), matchSize_of_wordWidth(width_type), LOAD_MATCH_BEFORE))
+            if (instrDataMatch(cur_privilege, virtaddr_bits(vaddr), zero_extend(0b0), matchSize_of_wordWidth(width_type), LOAD_MATCH_BEFORE))
             then { return RETIRE_FAIL }
             else if check_misaligned(vaddr, width_type)
             then { handle_mem_exception(vaddr, E_Load_Addr_Align()); return RETIRE_FAIL }
@@ -364,7 +364,7 @@ function process_vlsseg (nf, vm, vd, load_width_bytes, rs1, rs2, EMUL_pow, num_e
                 match mem_read(Read(Data), paddr, load_width_bytes, false, false, false) {
                   MemValue(elem)   => {
                     if (xlen_bytes >= load_width_bytes) then {
-                      let load_after_match : bool = instrDataMatch(cur_privilege, zero_extend(vaddr), zero_extend(elem), matchSize_of_wordWidth(width_type), LOAD_MATCH_AFTER);
+                      let load_after_match : bool = instrDataMatch(cur_privilege, virtaddr_bits(vaddr), zero_extend(elem), matchSize_of_wordWidth(width_type), LOAD_MATCH_AFTER);
                     };
                     write_single_element(load_width_bytes * 8, i, vd + to_bits(5, j * EMUL_reg), elem)
                   },
@@ -430,7 +430,7 @@ function process_vssseg (nf, vm, vs3, load_width_bytes, rs1, rs2, EMUL_pow, num_
           Ext_DataAddr_Error(e)  => { ext_handle_data_check_error(e); return RETIRE_FAIL },
           Ext_DataAddr_OK(vaddr) => {
             if (xlen_bytes >= load_width_bytes) then {
-              trigMatched = instrDataMatch(cur_privilege, zero_extend(vaddr), zero_extend(dbg_elem_val), matchSize_of_wordWidth(width_type), STORE_MATCH);
+              trigMatched = instrDataMatch(cur_privilege, virtaddr_bits(vaddr), zero_extend(dbg_elem_val), matchSize_of_wordWidth(width_type), STORE_MATCH);
             };
             if (trigMatched)
             then { return RETIRE_FAIL }
@@ -507,7 +507,7 @@ function process_vlxseg (nf, vm, vd, EEW_index_bytes, EEW_data_bytes, EMUL_index
         match ext_data_get_addr(rs1, to_bits(xlen, elem_offset), Read(Data), EEW_data_bytes) {
           Ext_DataAddr_Error(e)  => { ext_handle_data_check_error(e); return RETIRE_FAIL },
           Ext_DataAddr_OK(vaddr) =>
-            if (instrDataMatch(cur_privilege, zero_extend(vaddr), zero_extend(0b0), matchSize_of_wordWidth(width_type), LOAD_MATCH_BEFORE))
+            if (instrDataMatch(cur_privilege, virtaddr_bits(vaddr), zero_extend(0b0), matchSize_of_wordWidth(width_type), LOAD_MATCH_BEFORE))
             then { return RETIRE_FAIL }
             else if check_misaligned(vaddr, width_type)
             then { handle_mem_exception(vaddr, E_Load_Addr_Align()); return RETIRE_FAIL }
@@ -517,7 +517,7 @@ function process_vlxseg (nf, vm, vd, EEW_index_bytes, EEW_data_bytes, EMUL_index
                 match mem_read(Read(Data), paddr, EEW_data_bytes, false, false, false) {
                   MemValue(elem)   => {
                     if (xlen_bytes >= EEW_data_bytes) then {
-                      let load_after_match : bool = instrDataMatch(cur_privilege, zero_extend(vaddr), zero_extend(elem), matchSize_of_wordWidth(width_type), LOAD_MATCH_AFTER);
+                      let load_after_match : bool = instrDataMatch(cur_privilege, virtaddr_bits(vaddr), zero_extend(elem), matchSize_of_wordWidth(width_type), LOAD_MATCH_AFTER);
                     };
                     write_single_element(EEW_data_bytes * 8, i, vd + to_bits(5, j * EMUL_data_reg), elem)
                   },
@@ -608,7 +608,7 @@ function process_vsxseg (nf, vm, vs3, EEW_index_bytes, EEW_data_bytes, EMUL_inde
           Ext_DataAddr_Error(e)  => { ext_handle_data_check_error(e); return RETIRE_FAIL },
           Ext_DataAddr_OK(vaddr) => {
             if (xlen_bytes >= EEW_data_bytes) then {
-              trigMatched = instrDataMatch(cur_privilege, zero_extend(vaddr), zero_extend(dbg_elem_val), matchSize_of_wordWidth(width_type), STORE_MATCH);
+              trigMatched = instrDataMatch(cur_privilege, virtaddr_bits(vaddr), zero_extend(dbg_elem_val), matchSize_of_wordWidth(width_type), STORE_MATCH);
             };
             if (trigMatched)
             then { return RETIRE_FAIL }
@@ -706,7 +706,7 @@ function process_vlre (nf, vd, load_width_bytes, rs1, elem_per_reg) = {
       match ext_data_get_addr(rs1, to_bits(xlen, elem_offset), Read(Data), load_width_bytes) {
         Ext_DataAddr_Error(e)  => { ext_handle_data_check_error(e); return RETIRE_FAIL },
         Ext_DataAddr_OK(vaddr) =>
-          if (instrDataMatch(cur_privilege, zero_extend(vaddr), zero_extend(0b0), matchSize_of_wordWidth(width_type), LOAD_MATCH_BEFORE))
+          if (instrDataMatch(cur_privilege, virtaddr_bits(vaddr), zero_extend(0b0), matchSize_of_wordWidth(width_type), LOAD_MATCH_BEFORE))
           then { return RETIRE_FAIL }
           else if check_misaligned(vaddr, width_type)
           then { handle_mem_exception(vaddr, E_Load_Addr_Align()); return RETIRE_FAIL }
@@ -716,7 +716,7 @@ function process_vlre (nf, vd, load_width_bytes, rs1, elem_per_reg) = {
               match mem_read(Read(Data), paddr, load_width_bytes, false, false, false) {
                 MemValue(elem)   => {
                   if (xlen_bytes >= load_width_bytes) then {
-                    let load_after_match : bool = instrDataMatch(cur_privilege, zero_extend(vaddr), zero_extend(elem), matchSize_of_wordWidth(width_type), LOAD_MATCH_AFTER);
+                    let load_after_match : bool = instrDataMatch(cur_privilege, virtaddr_bits(vaddr), zero_extend(elem), matchSize_of_wordWidth(width_type), LOAD_MATCH_AFTER);
                   };
                   write_single_element(load_width_bytes * 8, i, vd + to_bits(5, cur_field), elem)
                 },
@@ -737,7 +737,7 @@ function process_vlre (nf, vd, load_width_bytes, rs1, elem_per_reg) = {
       match ext_data_get_addr(rs1, to_bits(xlen, elem_offset), Read(Data), load_width_bytes) {
         Ext_DataAddr_Error(e)  => { ext_handle_data_check_error(e); return RETIRE_FAIL },
         Ext_DataAddr_OK(vaddr) =>
-          if (instrDataMatch(cur_privilege, zero_extend(vaddr), zero_extend(0b0), matchSize_of_wordWidth(width_type), LOAD_MATCH_BEFORE))
+          if (instrDataMatch(cur_privilege, virtaddr_bits(vaddr), zero_extend(0b0), matchSize_of_wordWidth(width_type), LOAD_MATCH_BEFORE))
           then { return RETIRE_FAIL }
           else if check_misaligned(vaddr, width_type)
           then { handle_mem_exception(vaddr, E_Load_Addr_Align()); return RETIRE_FAIL }
@@ -799,7 +799,7 @@ function process_vsre (nf, load_width_bytes, rs1, vs3, elem_per_reg) = {
         Ext_DataAddr_Error(e)  => { ext_handle_data_check_error(e); return RETIRE_FAIL },
         Ext_DataAddr_OK(vaddr) => {
           if (xlen_bytes >= load_width_bytes) then {
-            trigMatched = instrDataMatch(cur_privilege, zero_extend(vaddr), zero_extend(dbg_elem_val), matchSize_of_wordWidth(width_type), STORE_MATCH);
+            trigMatched = instrDataMatch(cur_privilege, virtaddr_bits(vaddr), zero_extend(dbg_elem_val), matchSize_of_wordWidth(width_type), STORE_MATCH);
           };
           if (trigMatched)
           then { return RETIRE_FAIL }
@@ -840,7 +840,7 @@ function process_vsre (nf, load_width_bytes, rs1, vs3, elem_per_reg) = {
         Ext_DataAddr_Error(e)  => { ext_handle_data_check_error(e); return RETIRE_FAIL },
         Ext_DataAddr_OK(vaddr) => {
           if (xlen_bytes >= load_width_bytes) then {
-            trigMatched = instrDataMatch(cur_privilege, zero_extend(vaddr), zero_extend(vs3_val[i]), matchSize_of_wordWidth(width_type), STORE_MATCH);
+            trigMatched = instrDataMatch(cur_privilege, virtaddr_bits(vaddr), zero_extend(vs3_val[i]), matchSize_of_wordWidth(width_type), STORE_MATCH);
           };
           if (trigMatched)
           then { return RETIRE_FAIL }
@@ -912,7 +912,7 @@ function process_vm(vd_or_vs3, rs1, num_elem, evl, op) = {
         match ext_data_get_addr(rs1, to_bits(xlen, i), Read(Data), 1) {
           Ext_DataAddr_Error(e)  => { ext_handle_data_check_error(e); return RETIRE_FAIL },
           Ext_DataAddr_OK(vaddr) =>
-            if (instrDataMatch(cur_privilege, zero_extend(vaddr), zero_extend(0b0), matchSize_of_wordWidth(width_type), LOAD_MATCH_BEFORE))
+            if (instrDataMatch(cur_privilege, virtaddr_bits(vaddr), zero_extend(0b0), matchSize_of_wordWidth(width_type), LOAD_MATCH_BEFORE))
             then { return RETIRE_FAIL }
             else if check_misaligned(vaddr, width_type)
             then { handle_mem_exception(vaddr, E_Load_Addr_Align()); return RETIRE_FAIL }
@@ -921,7 +921,7 @@ function process_vm(vd_or_vs3, rs1, num_elem, evl, op) = {
               TR_Address(paddr, _) => {
                 match mem_read(Read(Data), paddr, 1, false, false, false) {
                   MemValue(elem)   => {
-                    let load_after_match : bool = instrDataMatch(cur_privilege, zero_extend(vaddr), zero_extend(elem), matchSize_of_wordWidth(width_type), LOAD_MATCH_AFTER);
+                    let load_after_match : bool = instrDataMatch(cur_privilege, virtaddr_bits(vaddr), zero_extend(elem), matchSize_of_wordWidth(width_type), LOAD_MATCH_AFTER);
                     write_single_element(8, i, vd_or_vs3, elem)
                   },
                   MemException(e)  => { handle_mem_exception(vaddr, e); return RETIRE_FAIL }
@@ -933,7 +933,7 @@ function process_vm(vd_or_vs3, rs1, num_elem, evl, op) = {
         match ext_data_get_addr(rs1, to_bits(xlen, i), Write(Data), 1) {
           Ext_DataAddr_Error(e)  => { ext_handle_data_check_error(e); return RETIRE_FAIL },
           Ext_DataAddr_OK(vaddr) =>
-            if (instrDataMatch(cur_privilege, zero_extend(vaddr), zero_extend(vd_or_vs3_val[i]), matchSize_of_wordWidth(width_type), STORE_MATCH))
+            if (instrDataMatch(cur_privilege, virtaddr_bits(vaddr), zero_extend(vd_or_vs3_val[i]), matchSize_of_wordWidth(width_type), STORE_MATCH))
             then { return RETIRE_FAIL }
             else if check_misaligned(vaddr, width_type)
             then { handle_mem_exception(vaddr, E_SAMO_Addr_Align()); return RETIRE_FAIL }

diff --git a/model/riscv_insts_zicbom.sail b/model/riscv_insts_zicbom.sail
@@ -52,7 +52,7 @@ function process_clean_inval(rs1, cbop) = {
   match ext_data_get_addr(rs1, offset, Read(Data), cache_block_size) {
     Ext_DataAddr_Error(e) => { ext_handle_data_check_error(e); RETIRE_FAIL },
     Ext_DataAddr_OK(vaddr) => {
-      if (instrDataMatch(cur_privilege, zero_extend(vaddr), zero_extend(0b0), cacheBlockSize_to_matchSize(cache_block_size_exp), STORE_MATCH))
+      if (instrDataMatch(cur_privilege, virtaddr_bits(vaddr), zero_extend(0b0), cacheBlockSize_to_matchSize(cache_block_size_exp), STORE_MATCH))
       then { RETIRE_FAIL }
       else {
         let res: option(ExceptionType) = match translateAddr(vaddr, Read(Data)) {

diff --git a/model/riscv_insts_zicboz.sail b/model/riscv_insts_zicboz.sail
@@ -35,7 +35,7 @@ function clause execute(RISCV_ZICBOZ(rs1)) = {
     match ext_data_get_addr(rs1, offset, Write(Data), cache_block_size) {
       Ext_DataAddr_Error(e) => { ext_handle_data_check_error(e); RETIRE_FAIL },
       Ext_DataAddr_OK(vaddr) => {
-        if (instrDataMatch(cur_privilege, zero_extend(vaddr), zero_extend(0b0), cacheBlockSize_to_matchSize(cache_block_size_exp), STORE_MATCH))
+        if (instrDataMatch(cur_privilege, virtaddr_bits(vaddr), zero_extend(0b0), cacheBlockSize_to_matchSize(cache_block_size_exp), STORE_MATCH))
         then { RETIRE_FAIL }
         else {
           // "An implementation may update the bytes in any order and with any granularity