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Add support for Zc* extensions (#107)
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liweiwei90 authored Nov 17, 2022
1 parent 9f4d2be commit 8df0274
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10 changes: 9 additions & 1 deletion constants.py
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isa_regex = \
re.compile("^RV(32|64|128)[IE]+[ABCDEFGHJKLMNPQSTUVX]*(Zicsr|Zifencei|Zihintpause|Zam|Ztso|Zkne|Zknd|Zknh|Zkse|Zksh|Zkg|Zkb|Zkr|Zks|Zkn|Zba|Zbc|Zbb|Zbp|Zbr|Zbm|Zbs|Zbe|Zbf|Zbt|Zmmul|Zbpbo){,1}(_Zicsr){,1}(_Zifencei){,1}(_Zihintpause){,1}(_Zmmul){,1}(_Zam){,1}(_Zba){,1}(_Zbb){,1}(_Zbc){,1}(_Zbe){,1}(_Zbf){,1}(_Zbm){,1}(_Zbp){,1}(_Zbpbo){,1}(_Zbr){,1}(_Zbs){,1}(_Zbt){,1}(_Zkb){,1}(_Zkg){,1}(_Zkr){,1}(_Zks){,1}(_Zkn){,1}(_Zknd){,1}(_Zkne){,1}(_Zknh){,1}(_Zkse){,1}(_Zksh){,1}(_Ztso){,1}$")
re.compile("^RV(32|64|128)[IE]+[ABCDEFGHJKLMNPQSTUVX]*(Zicsr|Zifencei|Zihintpause|Zam|Ztso|Zkne|Zknd|Zknh|Zkse|Zksh|Zkg|Zkb|Zkr|Zks|Zkn|Zba|Zbc|Zbb|Zbp|Zbr|Zbm|Zbs|Zbe|Zbf|Zbt|Zmmul|Zbpbo|Zca|Zcf|Zcd|Zcb|Zcmp|Zcmt){,1}(_Zicsr){,1}(_Zifencei){,1}(_Zihintpause){,1}(_Zmmul){,1}(_Zam){,1}(_Zba){,1}(_Zbb){,1}(_Zbc){,1}(_Zbe){,1}(_Zbf){,1}(_Zbm){,1}(_Zbp){,1}(_Zbpbo){,1}(_Zbr){,1}(_Zbs){,1}(_Zbt){,1}(_Zkb){,1}(_Zkg){,1}(_Zkr){,1}(_Zks){,1}(_Zkn){,1}(_Zknd){,1}(_Zkne){,1}(_Zknh){,1}(_Zkse){,1}(_Zksh){,1}(_Ztso){,1}(_Zca){,1}(_Zcf){,1}(_Zcd){,1}(_Zcb){,1}(_Zcmp){,1}(_Zcmt){,1}$")

# regex to find <msb>..<lsb>=<val> patterns in instruction
fixed_ranges = re.compile(
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(0x00A, 'vxrm'),
(0x00F, 'vcsr'),
(0x015, 'seed'), # Zkr
(0x017, 'jvt'), # Zcmt

# Standard User RO
(0xC00, 'cycle'),
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arg_lut['c_uimm9sphi'] = (12, 12)
arg_lut['c_uimm10sp_s'] = (12,7)
arg_lut['c_uimm9sp_s'] = (12,7)
arg_lut['c_uimm2'] = (6, 5)
arg_lut['c_uimm1'] = (5, 5)
arg_lut['c_rlist'] = (7, 4)
arg_lut['c_spimm'] = (3, 2)
arg_lut['c_index'] = (9, 2)

arg_lut['rs1_p'] = (9,7)
arg_lut['rs2_p'] = (4,2)
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arg_lut['c_rs2_n0'] = (6,2)
arg_lut['c_rs1_n0'] = (11,7)
arg_lut['c_rs2'] = (6,2)
arg_lut['c_sreg1'] = (9,7)
arg_lut['c_sreg2'] = (4,2)

# dictionary containing the mapping of the argument to the what the fields in
# the latex table should be
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7 changes: 7 additions & 0 deletions encoding.h
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#define MSTATEEN0_CS 0x00000001
#define MSTATEEN0_FCSR 0x00000002
#define MSTATEEN0_JVT 0x00000004
#define MSTATEEN0_HCONTEXT 0x0200000000000000
#define MSTATEEN0_HENVCFG 0x4000000000000000
#define MSTATEEN_HSTATEEN 0x8000000000000000
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#define HSTATEEN0_CS 0x00000001
#define HSTATEEN0_FCSR 0x00000002
#define HSTATEEN0_JVT 0x00000004
#define HSTATEEN0_SCONTEXT 0x0200000000000000
#define HSTATEEN0_SENVCFG 0x4000000000000000
#define HSTATEEN_SSTATEEN 0x8000000000000000
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#define SSTATEEN0_CS 0x00000001
#define SSTATEEN0_FCSR 0x00000002
#define SSTATEEN0_JVT 0x00000004

#define MSECCFG_MML 0x00000001
#define MSECCFG_MMWP 0x00000002
#define MSECCFG_RLB 0x00000004
#define MSECCFG_USEED 0x00000100
#define MSECCFG_SSEED 0x00000200

/* jvt fields */
#define JVT_MODE 0x3F
#define JVT_BASE (~0x3F)

#define PRV_U 0
#define PRV_S 1
#define PRV_M 3
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1 change: 1 addition & 0 deletions rv64_zcb
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c.zext.w rd_rs1_p 1..0=1 15..13=4 12..10=7 6..5=3 4..2=4
11 changes: 11 additions & 0 deletions rv_zcb
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c.lbu rd_p rs1_p c_uimm2 1..0=0 15..13=4 12..10=0
c.lhu rd_p rs1_p c_uimm1 1..0=0 15..13=4 12..10=1 6=0
c.lh rd_p rs1_p c_uimm1 1..0=0 15..13=4 12..10=1 6=1
c.sb rs2_p rs1_p c_uimm2 1..0=0 15..13=4 12..10=2
c.sh rs2_p rs1_p c_uimm1 1..0=0 15..13=4 12..10=3 6=0
c.zext.b rd_rs1_p 1..0=1 15..13=4 12..10=7 6..5=3 4..2=0
c.sext.b rd_rs1_p 1..0=1 15..13=4 12..10=7 6..5=3 4..2=1
c.zext.h rd_rs1_p 1..0=1 15..13=4 12..10=7 6..5=3 4..2=2
c.sext.h rd_rs1_p 1..0=1 15..13=4 12..10=7 6..5=3 4..2=3
c.not rd_rs1_p 1..0=1 15..13=4 12..10=7 6..5=3 4..2=5
c.mul rd_rs1_p rs2_p 1..0=1 15..13=4 12..10=7 6..5=2
6 changes: 6 additions & 0 deletions rv_zcmp
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cm.push c_rlist c_spimm 1..0=2 15..13=5 12..8=0x18
cm.pop c_rlist c_spimm 1..0=2 15..13=5 12..8=0x1A
cm.popretz c_rlist c_spimm 1..0=2 15..13=5 12..8=0x1C
cm.popret c_rlist c_spimm 1..0=2 15..13=5 12..8=0x1E
cm.mvsa01 c_sreg1 c_sreg2 1..0=2 15..13=5 12..10=3 6..5=1
cm.mva01s c_sreg1 c_sreg2 1..0=2 15..13=5 12..10=3 6..5=3
1 change: 1 addition & 0 deletions rv_zcmt
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cm.jalt c_index 1..0=2 15..13=5 12..10=0

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