Merge branch 'tariqkurd-repo/master'

arg_lut.csv

@@ -2,6 +2,7 @@
 "rt", 19, 15
 "rs1", 19, 15
 "rs2", 24, 20
+"rs2_n0", 24, 20
 "rs3", 31, 27
 "aqrl", 26, 25
 "aq", 26, 26

constants.py

@@ -14,6 +14,7 @@
     "c_mv": {"c_jr"},
     "c_jalr": {"c_ebreak"},
     "c_add": {"c_ebreak", "c_jalr"},
+    "cadd": {"cmv"}
 }
 
 isa_regex = re.compile(

csrs.csv

@@ -60,6 +60,7 @@
 0x142, "scause"
 0x143, "stval"
 0x144, "sip"
+0x14b, "stval2"
 0x14D, "stimecmp"
 0x14E, "sctrctl"
 0x14F, "sctrstatus"
@@ -83,6 +84,7 @@
 0x242, "vscause"
 0x243, "vstval"
 0x244, "vsip"
+0x24b, "vstval2"
 0x24D, "vstimecmp"
 0x24E, "vsctrctl"
 0x250, "vsiselect"
@@ -94,6 +96,9 @@
 0x257, "vsireg6"
 0x25C, "vstopei"
 0x280, "vsatp"
+0x480, "utid"
+0x580, "stid"
+0x780, "mtid"
 0x600, "hstatus"
 0x602, "hedeleg"
 0x603, "hideleg"
@@ -246,6 +251,7 @@
 0x3ed, "pmpaddr61"
 0x3ee, "pmpaddr62"
 0x3ef, "pmpaddr63"
+0x416, "ddc"
 0x747, "mseccfg"
 0x7a0, "tselect"
 0x7a1, "tdata1"
@@ -259,6 +265,8 @@
 0x7b1, "dpc"
 0x7b2, "dscratch0"
 0x7b3, "dscratch1"
+0x7bc, "dddc"
+0x7bd, "dinfcap"
 0xB00, "mcycle"
 0xB02, "minstret"
 0xB03, "mhpmcounter3"

extensions/unratified/rv64_cheri

@@ -0,0 +1,52 @@
+lc                rd rs1          imm12   14..12=4 6..2=0x03 1..0=3
+sc                imm12hi rs1 rs2 imm12lo 14..12=4 6..2=0x08 1..0=3
+
+#next to ADDIW
+caddi             rd rs1          imm12   14..12=2 6..2=0x06 1..0=3
+
+#5-bit immediate and 25 says whether to shift it
+scbndsi           rd rs1 imm5 31..26=1    14..12=5 6..2=0x04 1..0=3
+
+#if rs2=x0 decode as cmove
+cadd              rd rs1 rs2_n0     31..25=6 14..12=0 6..2=0x0C 1..0=3
+cmv               rd rs1 24..20=0x0 31..25=6 14..12=0 6..2=0x0C 1..0=3
+scaddr            rd rs1 rs2      31..25=6 14..12=1 6..2=0x0C 1..0=3
+acperm            rd rs1 rs2      31..25=6 14..12=2 6..2=0x0C 1..0=3
+schi              rd rs1 rs2      31..25=6 14..12=3 6..2=0x0C 1..0=3
+sceq              rd rs1 rs2      31..25=6 14..12=4 6..2=0x0C 1..0=3
+cbld              rd rs1 rs2      31..25=6 14..12=5 6..2=0x0C 1..0=3
+scss              rd rs1 rs2      31..25=6 14..12=6 6..2=0x0C 1..0=3
+scmode            rd rs1 rs2      31..25=6 14..12=7 6..2=0x0C 1..0=3
+
+scbnds            rd rs1 rs2      31..25=7 14..12=0 6..2=0x0C 1..0=3
+scbndsr           rd rs1 rs2      31..25=7 14..12=1 6..2=0x0C 1..0=3
+
+gctag             rd rs1 31..25=8 24..20=0 14..12=0 6..2=0x0C 1..0=3
+gcperm            rd rs1 31..25=8 24..20=1 14..12=0 6..2=0x0C 1..0=3
+gctype            rd rs1 31..25=8 24..20=2 14..12=0 6..2=0x0C 1..0=3
+gcmode            rd rs1 31..25=8 24..20=3 14..12=0 6..2=0x0C 1..0=3
+gchi              rd rs1 31..25=8 24..20=4 14..12=0 6..2=0x0C 1..0=3
+gcbase            rd rs1 31..25=8 24..20=5 14..12=0 6..2=0x0C 1..0=3
+gclen             rd rs1 31..25=8 24..20=6 14..12=0 6..2=0x0C 1..0=3
+cram              rd rs1 31..25=8 24..20=7 14..12=0 6..2=0x0C 1..0=3
+sentry            rd rs1 31..25=8 24..20=8 14..12=0 6..2=0x0C 1..0=3
+
+modesw.cap        31..25=9  24..15=0 14..12=1 11..7=0 6..2=0x0C 1..0=3
+modesw.int        31..25=10 24..15=0 14..12=1 11..7=0 6..2=0x0C 1..0=3
+
+#adjacent to sh[123]add
+sh4add     rd rs1 rs2 31..25=16 14..12=7 6..2=0x0C 1..0=3
+
+#adjacent to sh[123]add.uw
+sh4add.uw  rd rs1 rs2 31..25=16 14..12=7 6..2=0x0E 1..0=3
+
+#regular encodings - will become a separate extension
+lr.b        rd rs1 24..20=0 aq rl 31..29=0 28..27=2 14..12=0 6..2=0x0B 1..0=3
+lr.h        rd rs1 24..20=0 aq rl 31..29=0 28..27=2 14..12=1 6..2=0x0B 1..0=3
+sc.b        rd rs1 rs2      aq rl 31..29=0 28..27=3 14..12=0 6..2=0x0B 1..0=3
+sc.h        rd rs1 rs2      aq rl 31..29=0 28..27=3 14..12=1 6..2=0x0B 1..0=3
+
+#regular encodings for double width datatype
+amoswap.c   rd rs1 rs2      aq rl 31..29=0 28..27=1 14..12=4 6..2=0x0B 1..0=3
+lr.c        rd rs1 24..20=0 aq rl 31..29=0 28..27=2 14..12=4 6..2=0x0B 1..0=3
+sc.c        rd rs1 rs2      aq rl 31..29=0 28..27=3 14..12=4 6..2=0x0B 1..0=3